Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

CNN-3d-lensfree

Département Microtechnologies pour la Biologie et la Santé (LETI)

Laboratoire Imagerie et Systèmes d'Acquisition

01-09-2019

SL-DRT-19-0605

lionel.herve@cea.fr

At CEA-Leti, we are developing lensfree microscopy for the monitoring of cell culture. This technique overpass several limits of conventional microscopy (compactness, field of view, quantification, etc.). Recently we showed, for the first time, 3D+time acquisitions of 3D cell culture with a lens-free microscope. We observed cells without any labelling within the volume as large as several cubic millimeters over several days. This new mean of microscopy allowed us to observe a broad range of phenomena only present in 3D environments. However, two drawbacks are still present on the microscope prototype: a long reconstruction time (>1 hour/frame) and the reconstructed volumes present artefacts owing to the limited number of angular acquisitions. The thesis work will focus on the ability of deep learning technologies to overcome the above-mentioned limitations. Basically, a convolutional neural network will be trained on the basis of simulated 3D cell culture volume (ground truth) and simulated response of our current 3D lensfree microscope (input). This approach is expected to accelerate the reconstruction process and to allow full 3D reconstructions. Yet it poses two scientific questions: are simulated data pertinent to train a neural network and how can we assess the quality of 3D reconstruction obtained through a neural network? Profile of the candidate sought: - Engineering degree in applied mathematics or physical sciences. - Strong knowledge in image processing with skills in deep learning.

Resistant and resilient processor to fault attacks and side-channel attacks

Département Systèmes

Laboratoire Sécurité des Objets et des Systèmes Physiques

01-09-2019

SL-DRT-19-0608

olivier.savry@cea.fr

Crypto-processors are not the only ones that are sensitive to fault attacks and side-channel attacks, CPUs are also prone to those flaws. Unfortunately, their sensitivities to these threats are poorly known. The objective of this thesis will be to characterize the consequences of these faults and leaks. New horizontal-type side-channel attacks based on machine learning can be experimented to go back to the executed code. Based on this knowledge, the PhD student will implement a processor core on FPGA completely resistant to intentional faults and side-channel attacks. Fault countermeasures solutions are often based on redundancy (spatial and temporal redundancy, error detector and corrector code, ...) that only increase the leakage and therefore the vulnerability to side-channel attacks. This approach is innovative as it aims to resolve this dilemma. The detection of faults is not the only constraint to be taken into account, however, it will be necessary to ensure that the CPU is resilient and able to restart from a stable state as close as possible to the erroneous state.

3D Thermomechanical Modeling of Printed Circuit Boards

DLORR

01-09-2019

SL-DRT-19-0623

manuel.fendler@cea.fr

The digital transition is illustrated in the factory of the future by the instrumentation of tools and parts evolving in extremely harsh environments for the Internet of Things. In order to ensure an efficient and robust integration, the study proposed in the context of this thesis aims to acquire knowledge of design constraints, and to implement the modeling and simulation tools that allow the collaborative mechanical and electronical design of future intelligent industrial systems

Electronic packaging by cold spray metallic encapsulation

DLORR

01-09-2019

SL-DRT-19-0624

manuel.fendler@cea.fr

The digital transition is illustrated in the factory of the future by the instrumentation of tools and parts evolving in extremely harsh environments for the Internet of Things. One of the difficulties is to integrate wireless communicating functions inside metallic parts, in particular for purposes of traceability with RFID tags. Due to the difficulties associated with the delicate electromagnetic environment, there are no integration solutions in the state of the art. The aim of this study is to investigate the potentialities offered by the Cold Spray technique, by characterizing the beneficial effects of texture on the metal absorption properties thus implemented to encapsulate the electronic chip.

Tools and methods for securing a memory hierarchy against software side-channel attacks

Département Systèmes

Laboratoire Sécurité des Objets et des Systèmes Physiques

01-10-2019

SL-DRT-19-0625

thomas.hiscock@cea.fr

Nowadays, computing systems execute an important quantity of untrusted software and have to isolate them from other user-trusted applications. For such multi-applications environments, strong process isolation is mandatory for security. Indeed, it prevents malicious processes to read or modify data of legitimate ones. In practice, perfect isolation is very difficult to achieve. Indeed, virtual memory or virtualisation are usually not sufficient: processes still execute on the same hardware and share lots micro-architectural elements. The memory hierarchy, from first level of caches to random access memory (RAM) represents without doubts the most important part of hardware shared between different processes and hence represents a large surface of attack. This is illustrated by many examples like cache attacks, known for more than a decade, software-induced faults in DRAM (Rowhammer) or information leakage through the MMU. Even the famous Spectre and Meltdown attacks revealed in 2018 rely on caches to extract sensible information. Since most of these vulnerabilities are known for years, a large panel of ?vulnerability-specific? countermeasures is available. However, no single solution covers all these vulnerabilities and the interaction of these countermeasures is not really studied. The first objective of this thesis is to develop new tools (statistical and/or simulation based) to reason about the security of the memory management hardware as a whole. These tools will form a solid basis to compare existing countermeasures taken from the state-of-the-art and combine them efficiently. Finally, a key contribution of the thesis will be to propose, design and evaluate possible countermeasures to secure the memory hierarchy.

Hardware security for post-quantum cryptography based on elliptic curve isogenies

DPACA (CTReg)

Autre

01-10-2019

SL-DRT-19-0626

simon.pontie@cea.fr

The main objective of this PhD thesis is to design protections to improve the security of SIKE (Supersingular Isogeny Key Encapsulation) implementations against side-channel and fault attacks. Walks in elliptic curve isogeny graphs can be used to establish a shared secret with a Diffie-Hellman protocol. SIKE is a key encapsulation suite based on this asymmetric cryptography. It is executed on conventional computer and is thought to be secure against an attack by a quantum computer. NIST has initiated a competitive "post-quantum" cryptography standardisation. These algorithms were built to avoid cryptanalysis. But, attackers may explore alternative attack methods that exploit physical access to implementation. Electromagnetic radiation analysis of deciphering or fault injection are examples of such attacks. There exist protections to hide secrets which used by implementations of classical cryptography. But, there are only few counter-measures to protect SIKE implementations and the threat of physical attacks against isogeny-based cryptography is not well known, up to now. This thesis will address these two problems. The PhD student will begin with studying SIKE protocol and existing implementations. He/She will have to identify existing physical attack propositions and to provide new attack methods. To refine the threat characterisation, he/she will build attack demonstrators based on side-channel analysis and/or fault injection. He/She will propose counter-measures that could be algorithmic, software or hardware methods to protect SIKE implementation. The SAS "Secure Architectures and Systems" research group is located close to Marseille (FRANCE). It is a joint CEA and EMSE team with state-of-art equipment to perform side-channel and fault attacks. PhD student supervisors are Nadia El-Mrabet (EMSE/SAS), Luca De Feo (UVSQ/CRYPTO) and Simon Pontié (CEA/SAS).

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