Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Architectures to Ensure the Functional Safety of Neural Network based Systems

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Silicium des Architectures Numériques

01-09-2019

SL-DRT-19-0296

adrian.evans@cea.fr

Neural networks are increasingly used in mission critical systems such as those used for image recognition in autonomous vehicles. These systems must comply with standards for functional safety, therefore it is essential to ensure they operate correctly in the presence of certain types of faults and that they can detect those faults which could result in dangerous situations. The same formal neural network can be implemented on different hardware platforms (CPUs, FPGAs, etc.), depending on the required performance. In some cases, implementations based on spike coding and neurons can result in significant power savings. It is well understood how to analyze and improve the reliability of classical digital circuits (micro-controllers, RAMs, etc.), however, these approaches are not directly applicable to neural networks, especially those using spike coding and analog neurons. The goal of this PhD thesis is to develop new approaches to improve the fault tolerance of spiking neural networks. As the first part of the thesis, new fault models and quantitative metrics to measure the correct operation of the system will be developed. Test cases using both classic coding and spiking networks will be prepared, to provide a reference for the studies. These will include cases using both off-line learning and unsupervised learning. Then the candidate will look for new techniques for detecting and managing faults in order to make the full system more robust. One avenue will be techniques for testing the system while it is operational (on-line test). Another research direction consists of studying how the architecture of the formal network and training data can be adapted to improve fault tolerance.

Nonlinear compressive imaging for machine learning

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Circuits Intégrés, Intelligents pour l'Image

01-10-2019

SL-DRT-19-0299

william.guicquero@cea.fr

In a context where the deployment of image sensors combined with computer vision tend to grow very quickly, the major challenges lie in information and signal processing. In the field of smart low-power sensors, the emerging breakthrough technology named Compressive Sensing is of major interest. In the case of embedded systems, autonomous decision-making becomes one of the core device feature while available resources (i.e., memory load, computing complexity and power consumption) remain highly limited. Indeed, the power consumption due to the sensor with dedicated signal processing is largely related to the overall data bandwidth and involved signal dimensionality. In particular, recent theoretical results demonstrate that standard Machine Learning approach can be advantageously applied in the compressed signal domain. However, those results are only restricted to the methods said as « linear », i.e. based on linear projections. The first objective of this PhD will thus be to properly identify theoretical limitations related to the combination of advanced Machine Learning with Compressive Sensing. It will aim at providing cutting-edge algorithm principles outperforming state-of-the-art tradeoffs between resources and inference accuracy. Thanks to a solid background in the laboratory on these fields of research, the goal of this thesis will be to evaluate the interest of introducing non-linearity during the acquisition process in order to improve the overall efficiency. This will help to define proper levers for smart sensor design enabling close-to-sensor context recognition (e.g., specific object detection with a highly limited hardware).

SPAD Imager for HDR ToF using multimodal data fusion

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Circuits Intégrés, Intelligents pour l'Image

01-10-2019

SL-DRT-19-0301

william.guicquero@cea.fr

Depth sensors are currently a very high trending topic. Indeed, in the fields of autonomous vehicles, portable electronic devices and the Internet of Things, new technology enablers now tend to provide handy 3D image data for future innovative end-user applications. There is a great diversity of 3D sensor types, either using passive imaging (depth from defocus, stereovision, phase pixels...) or using active imaging (ultrasounds, structured light, Time-of-Flight...). Each of these systems addresses specifications in terms of depth dynamic range (accuracy of the measurement versus maximum distance). In this thesis, we will study the specific case of Single Photon Avalanche Diodes (SPAD). Recent scientific results regarding this electro-photonic component demonstrate its relevance in the context of Time-of-Flight (ToF) imaging, especially in the case of integration in a 3D-stacked design flow exhibiting a pixel pitch of the order of ten micrometers. However, the nature of the data gathered by this type of component requires significant signal processing within the sensor to extract relevant information. This thesis will aim to revise traditional approaches related to histogram processing by directly extracting statistical features from raw data. Depending on the background and skills of the PhD candidate, two research axes would be investigated. First, on the hardware side, possible modifications of SPAD based sensor architecture in order to provide ?augmented? multi-modal information. Second, on the theoretical and algorithmic side, data fusion methods to improve the final reconstruction rendering of depth maps from sensed data.

DC-DC Power Converter at micro-Watt and millimeter scales

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

01-09-2019

SL-DRT-19-0314

antoni.quelel@cea.fr

The aim of the PhD is to develop compact (mm3) power supplies with high efficiency at low power delivery (nW to µW).

Study of 300-GHz electronically reconfigurable transmitarray antennas in monolithic technology

Département Systèmes

Laboratoire Antennes, Propagation, Couplage Inductif

01-12-2018

SL-DRT-19-0320

antonio.clemente@cea.fr

Due to the scarcity of electromagnetic spectrum resources and the need of broad bandwidth for high data-rate communications, the millimetre wave (mm-wave) and sub-THz bands from 30 to 350 GHz are very attractive for 5G and beyond 5G applications. In this context, high gain electronically reconfigurable antennas with beam-steering, multi-beam, and beam-forming capability are required in a huge number of emerging applications for radar, sensing, and communication systems (civil and military) typically ranging from C-band (4-8 GHz) to W-band (75-110 GHz). Typically composed of one or more radiant surfaces operating in transmission mode and illuminated by one or more focal sources, transmitarrays (also called discrete lens) are a recent cutting-edge antenna concept. Transmitarrays are realized using multilayer printed circuit technologies compatible with the integration of the active devices (diodes, MEMS, NEMS, semi-conductors, etc.). These devices can be used to control the electromagnetic field on the array aperture with excellent performances (bandwidth, cross-polarization level). CEA and IETR (university of Rennes I) have a very strong and unique expertise on transmitarray antennas. The previous realized studies form 2006 demonstrated the potentiality of transmitarrays in X-band (8-12 GHz), in Ka-band (28-40 GHz), and in V-band (50-70 GHz). The major scientific & technical innovations beyond the state-of-the-art are the following: first experimental demonstrations ? at world level ? (1) of highly efficient (70%) and highly directive (gain > 43 dBi) flat antennas at 300 GHz, (2) of ultra-flat transmitarray antennas, and (3) of self-alignment techniques for highly-directive flat antennas beyond 80 GHz.

Low Level Programming model for not "Von Neumann" architecture

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Infrastructure et Ateliers Logiciels pour Puces

01-10-2019

SL-DRT-19-0325

Henri-Pierre.Charles@cea.fr

Since the 60s the programming model used by processors is the "Von Neumann" model in which a processor will look for instructions and data to be processed in the same memory. Increasing the transistor density on a chip has increased its frequency but has produced a "bottleneck" to the memory that can not provide instructions and data at the same frequency : the memory wall. Many architectural solutions have been proposed to solve this bottleneck. One of the solutions we are studying is an architecture in which calculations are made in memory, without moving the data to the processor. The evaluation of this solution has shown impressive potential gains in speed (x10000) and energy (x30). To exploit this potential, it is necessary to change the programming model because the instructions will no longer be read in memory but generated by a processor that will drive one or more memory plane. The subject of the thesis will be the compilation of a high-level language to a flow of instructions interleaving processor instructions responsible for controlling and calculating addresses and instructions for controlling calculations in memory. This subject is a part of a bigger project in which we create a system composed of processor and computing memory.

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