Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

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Design of neural networks adapted to FHE and MPC

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire composants logiciels pour la Sûreté et la Sécurité des Systèmes

01-10-2019

SL-DRT-20-0388

aymen.boudguiga@cea.fr

Cyber security : hardware and sofware (.pdf)

In this thesis, the student will investigate the variety of scenarios in which homomorphic encryption provides a meaningful countermeasure to confidentiality threats applying to neural net systems. To do this, she/he will leverage on the many degrees of freedom in neural network design as well as homomorphic encryption scheme design to propose specialized networks and FHE-schemes efficiently working together. The candidate will attempt to push this application/FHE co-design strategy to its limits in order to notably: evaluate deep neural networks over encrypted data (input/output privacy), evaluate encrypted deep networks over clear or encrypted inputs (model/output privacy with optional input privacy). This will require to define an efficient FHE-neuron as well as to bring privacy-by-design at all stages of its lifecycle: from the unitary encrypted-domain execution of the neuron itself, to input-private and/or model-private evaluation of networks of that neuron, and then up to the training of networks of such neurons (over clear data). In addition, she/he will investigate the use of MPC for the same evaluations. Ideally, she/he will identify situations where using either FHE or MPC are more suitable for ensuring data confidentiality. In addition, synergies between FHE and MPC usage will be studied. Furthermore, implementing proof of concepts will provide clear experimental evidences of either the practicality of marrying a neural network technique with a specific homomorphic encryption or MPC scheme or measuring/estimating the remaining gap to achieve the evaluation of networks of practically relevant size and complexity.

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Proved simplification engine for software deductive verification

Département Ingénierie Logiciels et Systèmes (LIST)

Laboratoire pour la Sûreté du Logiciel

01-09-2020

SL-DRT-20-0396

loic.correnson@cea.fr

Cyber security : hardware and sofware (.pdf)

The Frama-C platform developped at CEA is dedicated to formally establish the absence of bugs in critical sofwares. It is used at an industrial scale in various domains, such as avionics and energy production plants. No asses such waranties on critical sofwares, it is necessary to automate the verfication process with proof assistants (Coq, PVS, HOL) and SMT solvers (Z3, CVC4, Alt-Ergo). However, for these techniques to be applicable on industrial codes, it is necessary to first simplify our proof objectives. Inside Frama-C, we have developped the Qed engine which is precisely in charge of building and simplifying logical formula. This engine was typically responsible for dramatic gains in performance for proving critical codes at Airbus, leading to the adoption of the approach in their production process. Since Qed early developments in 2015 the engine has been extended with many improvements with an increasing complexity. It now becomes difficult to certify that the engine remains sound and only produce valid simplifications. To this end, the subject of the thesis is to completely redesign the Qed engine with the Why-3 proof environment by specifying its simplification algorithms and formally verifying their correctness. Eventually, the extracted code from this Why-3 development will replace the existing engine inside Frama-C.

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Hardware countermeasure techniques of cryptographic algorithms exploiting in-memory computing

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Silicium des Architectures Numériques

01-10-2020

SL-DRT-20-0401

simone.bacles-min@cea.fr

Cyber security : hardware and sofware (.pdf)

The LISAN Laboratory (Digital Design & Architecture Laboratory) develops and designs innovative chip systems based on multicore architectures and low-power architectures dedicated to the Internet of Things (IoT). The field of IoT overcomes many prerequisites, especially in the area of security of autonomous connected objects in energy. New architectures are supposed to be the most energy efficient as possible. The implementation of IoT security must also be guided by the available energy without causing any security breach. An intelligent memory, called C-SRAM, able to perform in memory computing has been designed within the laboratory. The aim of the thesis is to study the possibilities of this memory from the point of view of security. The intrinsic properties of this intelligent memory make it possible to envisage the implementation of several algorithms and in particular new countermeasures against combined physical attacks (side-channels and faults).

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Integration of ULP neurons network based on Injection Locked Oscillators

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Gestion d'Energie Capteurs et Actionneurs

01-09-2020

SL-DRT-20-0418

franck.badets@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Neural Networks have demonstrated their superiority compared to Von Neumman computing machines for complex classification tasks. Embedding neural networks near the sensors (Edge IA) is a promising way to afford decision autonomy to sensor nodes. This could lead to a global decrease of the power consumption of sensor networks by decreasing the information rate between the nodes and the calculation center which will have also to provide a smaller amount of calculation. Decreasing the power consumption of neurones is a hot research topic as it is a key toward Edge IA. Beside digital implementations, some analog implementations are proposed, but these solutions are bulky and their power consumption is still high. The aim of the thesis work is to demonstrate the feasibility of the implementation of a neural network using Ultra Low Power Injection Locked Oscillators as neurones. Thesis work should lead to the silicon demonstration of learning ability of such networks. Applicant should have a good knowledge of statistical learning and neural networks in particular. He should have good knowledge of analog electronics. Theoretical study will necessitate strong expertise on both mathematics and modelling using python

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Advanced nanocomposites for additive manufacturing

Département des Technologies des NanoMatériaux (LITEN)

Laboratoire Synthèse et Intégration des Nanomatériaux

01-10-2020

SL-DRT-20-0419

thomas.pietri@cea.fr

Additive manufacturing, new routes for saving materials (.pdf)

The proposed scientific objectives are at the crossroads of nanomaterials and additive manufacturing. Various 3D printing technologies of polymeric matrices have been developed, allowing a conversion of a numerical model with a great precision. But, due to the very recent development of these technologies, the currently available materials appear insufficiently mature and require significant improvements. A great chance of success for properties enhancement could certainly come from the fabrication of advanced nanocomposites (through inclusion of nanomaterials within a polymeric matrix). The work that will be carried out during his PhD will take advantage of the synthesis and functionalization of one-dimensionnal nanomaterials (nanowires, nanotubes). After characterization of the intrinsic properties of the nanocomposites, printable wires will be produced and used with 3D printers. High performance nanocomposites will be used for the fabrication of 3D elements with high conduction of electricity and/or heat. Applications for health will also be considered.

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Study of dynamic degradation and reliability of advanced GaN on Si power devices

Département Composants Silicium (LETI)

Laboratoire de Caractérisation et Test Electrique

01-10-2020

SL-DRT-20-0430

william.vandendaele@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

GaN-on-Si based power devices are now considered as the next generation of mass market devices for high frequency & low looses power converters (DC/DC, AC/DC or DC/AC). In this vision, LETI is developing its own pîlot line of GaN on Si power devices (CMOS compatible) from the GaN epitaxy to the final power module. These devices are supposed to operate dynamically between high voltage stage (650V and below) and high current state (> 20A) at high frequencies (> 100kHz). Statics and dynamic performances being proved, it is worth of interest to test and study reliability of these devices under high voltage stress and high temperature as well as under practical swithching conditions (hard/soft/ZVS). These studies aim to understand the underlying physical degradation mechanisms arising under operating conditions and ultimately to stabilize the technologie for industrial technological transfer. The PhD student will be responsible of : - Finalizing exisiting dynamic setups and create new ones especially concerning on-wafer switching test (limitations/feasibility) - In Depth study of HEMT electrical parameters degradation (Ron, Vt, Sw?) as well as Diode parameters (Vf, Sw) during DC or AC stress to determine the root cause of the degradation leading to reliability reduction. - Determination of Switching SOA of GaN based devices from LETI as well as studying new acceleration factors such as duty factor or switching frequency - Localization and Identification of Failure point and understanding of the Failure root cause through FA studies (IR or visible camera + FIB/MEB studies) - Proposal of new technological solutions to overcome some early failures and low realiblity issues The PhD student will be curious, open minded and team worker.

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