Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Optimization of countermeasure insertion for the safety of Integrated Circuits.

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-10-2019

SL-DRT-19-0681

lilia.zaourar@cea.fr

Hardware Trojans (HTs) are malicious blocks inserted into Systems on Chip (SoC) by untrusted parties in the IC design/manufacturing flow. They have been identified as a realistic threat, among others to the car safety and military. HTs aim to change SoCs' behavior, ranging from denial of service, decreased reliability, to confidential information leakage. Such attacks lead to multi-billions dollars loss per year for the semiconductor industry. Countermeasures against HTs exist, divided into two categories: detection and prevention. Ten years of research have shown that detection is a very challenging task, knowing the stealthy nature of the threat and the multiple possible forms of HTs. Prevention consists in modifying the design flow to take into account security issues. Despite its potential cost, it represents a more effective way to overcome HT insertion. So-called Design-for-Hardware-Trust (DfHT) methods exist, with various goals and impacts on performance. The MOOSIC project proposes a framework dedicated to security that can be integrated into the conventional IC design flow. The goal is to take into account, as early in the design phase, both countermeasures against HTs and performance, to ensure that the SoC behavior is guaranteed despite untrusted IPs vendors or foundry. Towards this objective, the project envisions to establish and evaluate security properties and then integrate them during synthesis with multi-objective optimization techniques, which will be built on a mathematical modeling of the problem that takes into account both the performance and the HTs?effects. It is indeed necessary to find a good compromise between the level of security sought after and performance. The candidate will have to propose a complete mathematical model of the problem that supports all the constraints and objectives (security, area, frequency, consumption). He will then have to develop optimization algorithms to effectively solve the problem of insertion of countermeasures on conventional criteria (time, area, consumption). Finally, a validation of the methodology on simple first examples is envisaged as well as some test on industrial use cases improvement with some improvement if necessary. The thesis will take place at the CEA LIST LCE and will be led by the LIP6 / Sorbonne University in Paris.

Development and characterization of ferroelectric layers for the fabrication of FeFET transistors

Département Technologies Silicium (LETI)

Autre laboratoire

01-02-2019

SL-DRT-19-0682

nicolas.vaxelaire@cea.fr

Permanent progression of electronic devices requires that their components must be constantly adapted. The current memories are based on Phase Change Memory (PCM) architectures, but they need high power to work. The introduction of ferroelectric materials would enable to create memories working with lower voltages and therefore being more adapted to technologies requiring low consumption (mobile applications for instance). The main feature of these materials is their ability to keep a residual polarization at null field. This polarization can be reversed thanks to an external electric field. So, it is possible to match the two states of polarization with the two logical states of a transistor (?passing? and ?blocking?), fundamental element of the memories. This thesis aims to analyze this ferroelectric material to introduce them in future generations of memories. A bibliographic study will allow to set up a design of experiments to fabricate these layers by Atomic Layer Deposition (ALD). Next, these depositions will be characterized according to several factors like the ferroelectricity, the crystal structure or the composition. Optimal conditions to satisfy a high polarization of the material will be deducted from this analyze. The integration of the layers in the associated transistors will mark a second step of the thesis. This one will mainly allow to validate the proper functioning of this so-called transistors FeFET, but also to study the interface between the ferroelectric oxide and the canal of the transistor. This study of the interface, supported by thermodynamic and kinetic simulations, will ensure that the electric charges do not come to accumulate, which would impact the functioning of the transistor.

Analysis of mechanical constraints on transmission lines by instrumentation with sensitive materials

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Fiabilité et Intégration Capteur

01-09-2019

SL-DRT-19-0683

nicolas.gregis@cea.fr

Reflectometry is as old as electromagnetism itself and share the same principle with radar technologies. CEA LIST has been working on reflectometry to make it available for cable diagnosis through the use of signal processing algorithms and embedded hardware, such as FPGA or SoC. Nowadays, progress in this field opens new possibilities, like transforming cables in distributed sensors, especially for detection of mechanical constraints. This is even more possible by adding to the cable materials with both electromagnetical and mechanical effects, such as magnetostrictive layers. Previous work on the subject has shown great potential for this combination. Thus the objective of this thesis will be to design a new cable integrating materials sensible to mechanical constraints and reflectometry. First the work will focus on the study of the best material combined with signal processing methods and then the new design will be proposed and tested. For this PhD project a sound knowledge in the field of electromagnetics is mandatory. It is also expected that the candidate has some basic knowledge in the fields of reflectometry and magnetostriction which are the core technologies used in this PhD project. Additionnaly, a solid background in signal processing techniques will be necessary for both the modelling and the analysis of experimental results. Those skills will also be useful for preparing a potential technological application. An important part of this thesis will also rely on the design of experimental set-ups. It is therefore expected that the candidate has motivation for experimental work.

Study of DNA origami?surface interactions for application in lithography

Département Technologies Silicium (LETI)

Laboratoire

01-09-2019

SL-DRT-19-0684

raluca.tiron@cea.fr

In nanotechnology in general and semiconductor industry in particular, there is an ever increasing need for smaller and more complex features at an ever lower cost. Some examples of applications are sub-10 nm features for creation of FinFETs, lateral (horizontal) and vertical gate-all around nanowires, single electron transistors and advanced non-volatile memories (STT-RAM, MRAM, OxRAM, etc.). To address the challenge of patterning at sub-10 nm features novel patterning approaches must be envisioned. DNA (deoxyribonucleic acid), by virtue of its inherent small diameter (2 nm), tendency to self-organize into various different morphologies and its possibilities for functionalization, offers the possibility to realize both two- and three dimensional structures at nanometer scale. The goal of this PhD work is to demonstrate the feasibility of nanostructuring the surface of a substrate using DNA origami as a mask, with an ultimate resolution of a few nanometer, with a density that is above the current state of the art in semiconductor industry. The focus of the internship will lie on ever more complex features, while ensuring long-range order by conventional lithography guide patterns. The last part of the thesis consists of the effective transfer of the DNA pattern into the substrate.

Testing techniques for advanced test coverage criteria

Département Ingénierie Logiciels et Systèmes (LIST)

Laboratoire pour la Sûreté du Logiciel

01-02-2018

SL-DRT-19-0701

virgile.prevosto@cea.fr

Dealing with advanced test criteria is particularly important in safety critical applications. For instance, in regulated domains such as aeronautics, advanced coverage criteria are strict normative requirements that the tester must satisfy before delivering the software. In other domains, coverage criteria are recognized as a good practice for testing, and a key ingredient of test-driven development. While a large number of automated testing tools are available, they offer a limited scope of services (test coverage measurement or automatic test generation) and are restricted to few coverage criteria. The global goal of this PhD project is to improve software testing practice by ?bridging the gap between the potentialities offered by the huge body of academic work on (code-)coverage criteria on one side, and their limited tool support and use in the industry on the other side. It will include developing ? generic test generation methods and heuristics for coverage of test objectives in a unified and efficient way; developing sound and scalable solutions to minimize a test suite and to detect polluting test objectives, including infeasible, duplicate and subsumed ones, in order ?to optimize testing; developing ? methods for efficient test assessment?. The proposed techniques will be evaluated on real-life programs from open-source projects or provided by industrial partners. The PhD project will be realized in Software Reliability and Security Lab of the List institute of CEA Tech, and co-supervised by Nikolai Kosmatov and Virgile Prevosto. The candidate will have Master's degree, or equivalent, in Computer Science, preferably in Software Verification and Validation. A good knowledge of symbolic execution, static analysis and/or deductive verification can be a plus.

Development of hybrid supercapacitors with potassium

Département de l'Electricité et de l'Hydrogène pour les Transports (LITEN)

Laboratoire Prototypage et Procédés Composants

01-10-2019

SL-DRT-19-0703

benoit.chavillon@cea.fr

In the framework of new battery technologies done at the « Département de l'Electricité et de l'Hydrogène pour les Transports (LITEN) », a new hybrid supercapacitor system has been developed. This kind of supercapacitor is mounted with an electrode of battery and another electrode of supercapacitor. So, hybrid supercapacitor using potassium as a transport ion in the electrolyte were developed at CEA recently, these studies leading to a functional system with very intereesting starting performance. However, this system shows some operative problems during cycling which could be investigated only via characterization of materials used. These analyses could be XPS or Raman spectroscopy, microscopic observation by TEM or BEM, or X-ray diffraction. During this analysis work, a part of the thesis would be dedicated to material development and work about electrodes formulations and equilibrium with the aim of increasing system performance. PhD could also have a part of work, depending of project progress, about system optimisation via the study of gelification of electrolyte of bipolar system.

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