Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Design, simulation, fabrication and characterization of an innovative logic/memory CUBE for In-Memory-Computing

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-10-2019

SL-DRT-19-0747

francois.andrieu@cea.fr

For integrated circuits to be able to leverage the future ?data deluge? coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this ?memory wall? consists in processing the information in-situ, owing to In-Memory-Computing (IMC). However, today's existing memory technologies are ineffective to In-Memory compute billions of data items. Things may change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. CEA-LETI received a prestigious European ERC grant to support a 5 year project and 3 new PhD students on a new project. This project will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems. This project that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient integrated circuits. In this context, the PhD study is about the design, simulation, fabrication and characterization of an innovative logic/memory CUBE for In-Memory-Computing.

Hardware/Software co-design of countermeasures against fault injection attacks

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Infrastructure et Ateliers Logiciels pour Puces

01-09-2019

SL-DRT-19-0748

damien.courousse@cea.fr

The thesis will focus on the hardware/software co-design of countermeasures against physical attacks, in particular, fault injection attacks. We will aim at developping new securing solutions that can be applied to all software components whatever their algorithmic nature (e.g. contrary to cryptography-specific countermeasures), able to exploit hardware security properties if available on the target architecture. To do so, we will modify the processor micro-architecture, and exploit code transformation and optimization strategies of the compiler to design new countermeasures with a high security level and a low performance overhead. The thesis is supported by the ANR projet COFFI, starting february 2019 (duration 42 months).

Incorporating expert knowledge and linguistic resources in deep neural networks for multi-domain and multilingual adaptation

Département Intelligence Ambiante et Systèmes Interactifs (LIST)

Vision & Ingénierie des Contenus (SAC)

01-03-2019

SL-DRT-19-0750

nasredine.semmar@cea.fr

Recent deep learning architectures and algorithms have shown impressive results for several Natural Language Processing (NLP) tasks such as Named entity recognition, Part-of-Speech tagging, Dependency parsing and Semantic role labelling. The actual performance of certain NLP tools for English evaluated on in-domain data is close to human level, thanks to deep learning models trained on huge annotated datasets. Contrariwise, approaching human-level accuracy on more complex domains and low-resource languages is still a hard issue. The proposed subject aims to explore and experiment new approaches based on the integration of expert knowledge and available linguistic resources in deep neural networks in order to improve the performance of NLP tools for specialty areas and low-resource languages. We propose to tackle this issue along the following key aspects, as an extension of the research work already carried out at LVIC laboratory: - Taking into account heterogeneous expert knowledge and linguistic resources: Ontologies, Terminology databases, Lexicons, Named entity recognition rules, Dependency parsing recognition rules, etc. - Implementing a formalism to describe expert knowledge and linguistic resources in a multi-level representation. The objective is to define a structure in which the different types of expert knowledge and linguistic resources will be represented separately but the whole representation would be described in the same format (model). - Exploring new strategies for incorporating expert knowledge and linguistic resources in deep neural networks. The underlying idea is to propose an integration mechanism which can be adapted to each expert knowledge and linguistic resource.

Detection and location of faults in a multiconductor transmission line

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Fiabilité et Intégration Capteur

01-09-2019

SL-DRT-19-0758

moussa.kafal@cea.fr

The proper functioning of a distribution network depends on the ability to quickly detect the occurrence of faults, such as discharges, short circuits or the penetration of moisture in the cables. If the nature of these defects depends on the application context, the techniques used to detect them depend essentially on the ability to request a cable with test signals, and to monitor the appearance of response signals that would testify to the existence of a modification in the cables. While this approach is clear in the case of standard cables consisting of two conductors, the case of Multiconductor cables remains more complex to deal with. Indeed, applying test signals to a pair of conductors typically causes parasitic excitation of nearby conductors, because of the electromagnetic coupling that connects them. This phenomenon can considerably complicate the interpretation of the results of a test, by creating an ambiguity in the identification of the faulty driver, because several drivers can couple with those actually under test. In this thesis, the coupling will be considered as an opportunity, because it allows to probe a larger number of drivers at the same time. The intrinsic ambiguity of such a proposition can be removed by repeating the tests on several pairs of conductors. It then seems interesting to define optimum choice strategies of drivers to test to cover the largest number of neighboring drivers, without testing all possible combinations. In this sense, this proposal is parsimonious, introducing the concept of effective test surface covered from a pair of conductors. A promising decision strategy for identifying a failing driver is provided by Bayesian tree and graph-based approaches. These tools make it possible to cross the information obtained in order to identify an explanatory model, here the faulty driver. Among the advantages of this approach we can count on their ability to integrate qualitative information, such as the typology of the defect, and to provide a result formulated in terms of probabilities associated with each possible scenario, thus qualifying the interpretation of results and to assess their reliability, unlike purely numerical methods. It will then be necessary to carry out a preparatory work, making it possible to evaluate the probability a priori of observing parasitic signals from a fault on a neighboring conductor. This work will be based on the study of line theory and will provide the link between the physical aspects of Multiconductor propagation and the observables considered during the tests.

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