Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Analysis of mechanical constraints on transmission lines by instrumentation with sensitive materials

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Fiabilité et Intégration Capteur

01-09-2019

SL-DRT-19-0683

nicolas.gregis@cea.fr

Reflectometry is as old as electromagnetism itself and share the same principle with radar technologies. CEA LIST has been working on reflectometry to make it available for cable diagnosis through the use of signal processing algorithms and embedded hardware, such as FPGA or SoC. Nowadays, progress in this field opens new possibilities, like transforming cables in distributed sensors, especially for detection of mechanical constraints. This is even more possible by adding to the cable materials with both electromagnetical and mechanical effects, such as magnetostrictive layers. Previous work on the subject has shown great potential for this combination. Thus the objective of this thesis will be to design a new cable integrating materials sensible to mechanical constraints and reflectometry. First the work will focus on the study of the best material combined with signal processing methods and then the new design will be proposed and tested. For this PhD project a sound knowledge in the field of electromagnetics is mandatory. It is also expected that the candidate has some basic knowledge in the fields of reflectometry and magnetostriction which are the core technologies used in this PhD project. Additionnaly, a solid background in signal processing techniques will be necessary for both the modelling and the analysis of experimental results. Those skills will also be useful for preparing a potential technological application. An important part of this thesis will also rely on the design of experimental set-ups. It is therefore expected that the candidate has motivation for experimental work.

Testing techniques for advanced test coverage criteria

Département Ingénierie Logiciels et Systèmes (LIST)

Laboratoire pour la Sûreté du Logiciel

01-02-2018

SL-DRT-19-0701

virgile.prevosto@cea.fr

Dealing with advanced test criteria is particularly important in safety critical applications. For instance, in regulated domains such as aeronautics, advanced coverage criteria are strict normative requirements that the tester must satisfy before delivering the software. In other domains, coverage criteria are recognized as a good practice for testing, and a key ingredient of test-driven development. While a large number of automated testing tools are available, they offer a limited scope of services (test coverage measurement or automatic test generation) and are restricted to few coverage criteria. The global goal of this PhD project is to improve software testing practice by ?bridging the gap between the potentialities offered by the huge body of academic work on (code-)coverage criteria on one side, and their limited tool support and use in the industry on the other side. It will include developing ? generic test generation methods and heuristics for coverage of test objectives in a unified and efficient way; developing sound and scalable solutions to minimize a test suite and to detect polluting test objectives, including infeasible, duplicate and subsumed ones, in order ?to optimize testing; developing ? methods for efficient test assessment?. The proposed techniques will be evaluated on real-life programs from open-source projects or provided by industrial partners. The PhD project will be realized in Software Reliability and Security Lab of the List institute of CEA Tech, and co-supervised by Nikolai Kosmatov and Virgile Prevosto. The candidate will have Master's degree, or equivalent, in Computer Science, preferably in Software Verification and Validation. A good knowledge of symbolic execution, static analysis and/or deductive verification can be a plus.

Co-clustering for times series

DM2I (LIST)

Laboratoire d'Analyse des Données et d'Intelligence des Systèmes

01-09-2019

SL-DRT-19-0704

aurore.lomet@cea.fr

The co-clustering aims to identify homogeneous blocks of a data table by a joint clustering of rows and columns. For this purpose, the rows and columns of a datatable are reorganized simultaneously to discover the latent structure of the data. Among the developed methods, the probabilistic approach by latent block model (LBM) uses latent variables to define row and column clusters. In this thesis, we focus on the co-clustering of time series. These data have the particularity of being ordered (along the temporal axis). This notion of order has to be taken into account for the definition and the interpetation of clusters. To do this, a method, presented in the literature, considers time series as elementary functions in order to apply a latent block model after data pre-processing or its FunBlock extension. Another approach to be developed could combine signal processing with data mining. Indeed, it would be interesting to work on a signal transformation to extract relevant features. The LBM and its optimization algorithm (VEM, Variational Expectation Maximization, or SEM-Gibbs) can then be adapted if necessary. The development of a method based on signal distance matrices may be considered. In both cases, the clusters of the moments are ordered chronologically. Another clustering method to study consists of allowing different time ranges (to be defined) in the same blocks to feature engineering.

Embedded perception system for real time 4D scene analysis

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Adéquation Algorithmes Architecture

01-12-2019

SL-DRT-19-0712

stephane.chevobbe@cea.fr

With the growing number of autonomous systems the needs of environment perceptions explode in the embedded systems. These systems integrate a wide variety of sensors and of perception functions. They often model the near environment with a collection of mostly independent specific functions. The goal of this work is to design a new embedded perception system, taking advantage of several sensors and temporal measurements to generate a 3D model understandable by a higher-level application. It could, for example, generates a 3D mesh of a scene with semantic and dynamic information. The targeted application domain is the extended reality. Firstly, the candidate will develop a golden applicative 3D modeling pipeline based on the latest algorithms on a PC. Next, he will imagine and define a embedded system with several sensors and will adapt the algorithms to minimize the energy consumption and reduce the execution latency.

Strain engineering for 12nm FDSOI technology and beyond

Département technologies silicium (LETI)

Laboratoire

01-09-2019

SL-DRT-19-0720

shay.reboh@cea.fr

Strain engineering is a major tool to boost the performance of transistors. Tensile strain increases electron mobility and compression improves holes mobility. Hole mobility is also favored by the use of SiGe channel. In advanced FDSOI the co-integration of Si channels for nMOS and and SiGe channels for pMOS is done by the transformation of the top-Si layer into SiGe via Ge condensation. For this, an epitaxy of a SiGe is done on a selected Si area. During thermal oxidation, Ge atoms are rejected into the underlying Si layer. The buried-oxyde (BOX) of the SOI wafer acts as a diffusion barrier for Ge, the result is a local SiGe-On-Insulator (SGOI) substrate. The SiGe film is obtained such as it keeps the in-plane lattice parameter of Si and therefore is found under biaxial compressive strain in the plane of growth. Today, the condensation technique allows a co-integration of Si-based nMOS and compressively strained SiGe-based pMOS transistors. The Problem: when the cSiGe made by Ge-condensation is discontinued for the fabrication of the STI, a local elastic relaxation of the compressive stress close to the STI edge is naturally expected. However, experiments show more than elastic relaxation over large distance from the STI discontinuity causing a significant loss of compressive strain in the layer, and therefore, a lower contribution to the performance of devices. In summary, the physical mechanisms behind this behavior are unknown today and of major impact on advanced CMOS. This work is aimed to bring light on this subject and propose/develop technologycal solutions.

Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-10-2019

SL-DRT-19-0747

francois.andrieu@cea.fr

For integrated circuits to be able to leverage the future ?data deluge? coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this ?memory wall? consists in processing the information in-situ, owing to In-Memory-Computing (IMC). However, today's existing memory technologies are ineffective to In-Memory compute billions of data items. Things may change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. CEA-LETI received a prestigious European ERC grant to support a 5 year project and 3 new PhD students on a new project. This project will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems. This project that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient integrated circuits. In this context, the PhD study is about the design, simulation and characterization of an innovative logic/memory CUBE for In-Memory-Computing.

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