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Development of an InP HBT technology on silicon 200mm substrate for sub-mmW power amplifier applications for 6G wireless communications

Technological challenge: Emerging materials and processes for nanotechnologies and microelectronics (learn more)

Department: Département Composants Silicium (LETI)

Laboratory: Laboratoire Dispositifs Quantiques et Connectivité

Start Date: 01-09-2022

Location: Grenoble

CEA Code: SL-DRT-22-0718

Contact: herve.boutry@cea.fr

Following the roadmap for 6G, there is a clear trend to increase the frequency of communication systems in order to enlarge their bandwidth. In these new frequency bands, the highest at 250-325GHz represents the most challenging for technology manufacturers as silicon technologies and Gallium Nitride cannot present sufficient performances for power amplification, which is today a key limiter in an RF TxRx chain at sub-mmW frequencies. Indium Phosphide Heterojunction Bipolar Transistors (InP HBT) are identified by LETI as the most relevant device, combining high dynamic performance: FMAX (frequency at which the power gain is null) up to 1 THz and high breakdown voltage : 3.5/4V, linked to Psat and reliability. Being able to combine a logic core, RF generation and performant passives (B55X, BiCMOS technology) with power amplification (InP HBT) through 3D integration will enable performant and affordable chips at sub-mmW frequencies. The development of an InP HBT on Silicon substrate will provide lower cost, increased maturity and transferability to silicon technology providers. Proposed subject: The candidate will participate in the development of an InP HBT technology on silicon 200mm substrate in LETI, in collaboration with IEMN in Lille. She/He will define parts of the technology flow, follow batches progress in the clean room with support from LETI engineers. The candidate will participate in the DC and RF characterization campaigns both at LETI and IEMN (DC to 325GHz and above). Based on these results and on finite element simulations, She/He will propose process and layout optimization in order to increase the transistors performance to FMAX >500GHz, and beyond if possible (FMAX=1THz). This subject is very broad and includes III-V technology, electrical characterization and simulation.

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