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Micro-compilation for Ternary Neural Network on an In-Memory Computing architecture

Technological challenge: New computing paradigms, circuits and technologies, incl. quantum (learn more)

Department: Département d'Optronique (LETI)

Laboratory: Laboratoire conception de Circuits Intégrés Intelligents pour l'image

Start Date: 01-10-2022

Location: Grenoble

CEA Code: SL-DRT-22-0643

Contact: william.guicquero@cea.fr

Edge Artificial Intelligence and low-level Computer Vision is now massively deployed at the near-sensor level in order to further extend the capabilities of smart embedded imaging systems. Recent advances in Deep Learning show that low-precision neural networks (whose weights and activations are represented by only a few bits) tend to match their non-quantized counterparts in terms of inference accuracy. It can typically target application use cases such that low-power image detection or recognition as well as image/video compression. In addition, the use of such a reduced arithmetic demonstrates the advantage of being highly compatible with IMC (In-Memory Computing)-type architectures, thanks to the appropriate combination of massively parallelized logic with dedicated analog computing circuitry. This specific algorithm/architecture co-design typically yields an energy gain of several orders of magnitude over a conventional design approach. Based on recent work done at the CEA on low-power AI-dedicated hardware for smart imaging, this thesis project aims to develop an innovative programming model being dedicated to this type of IMC architecture. The objective here is to enable a far higher level of reconfigurability (enabling a wider range of Computer Vision tasks) with respect to the target neural network topology being mapped to the specific hardware. In order to benefit from the computing parallelization while limiting memory access costs, the compiler will aim at optimizing the execution scheduler as well as the distribution of computation tasks on the available memory. The thesis work will typically be partitioned as follow: - Sate-of the-art study and familiarization with the concepts of quantized neural networks in the context of image processing. - Handling the analysis tools allowing the automatic generation of NN-related computational graphs. - Identification of possible data organizations and computing adapted to IMC. - Programming of the dedicated compiler with its associated Hardware simulator.

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