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Cryo back-end of line for quantum application

Technological challenge: Emerging materials and processes for nanotechnologies and microelectronics (learn more)

Department: Département des Plateformes Technologiques (LETI)

Laboratory: Labo Support et Interface Techno

Start Date: 01-09-2022

Location: Grenoble

CEA Code: SL-DRT-22-0583

Contact: roselyne.segaud@cea.fr

Spin and superconducting Qbits require the development of short-distance metallic routing compatible with low temperature (below TC transition) and high frequency operations. This integration usually named Back-end of line connects devices (Qbit, resonator?) or cells (chip to chip). Nowadays, superconducting layer playing interconnection role are often made on Nb-base layer but processes and architecture are not aligned with advances nodes (C28 and C45 technologies). The aim is then to put in place innovative processes and integration and to study the behavior at room temperature but more specifically at cryogenic temperatures. Thus, screening of superconducting materials that fulfil integration demands and low temperature constrains will be proposed. The work will start with dry etching of selected superconducting layer that will rely on surface and interface studies up to their behavior one integrated into BEOL brick. The later will be based on smart architecture describe the DD21807/FR2112216 patent and will be implemented. On a second hand, mesocopic physics, confinement effect, and electrical transport will be carry out at high and low temperatures.

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