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Low-Temperature Characteristics of merging memory technologies for CMOS co-optimization and/or in-memory computing applications

Technological challenge: Artificial intelligence & Data intelligence (learn more)

Department: Département Composants Silicium (LETI)

Laboratory: Laboratoire de Caractérisation et Test Electrique

Start Date: 01-10-2022

Location: Grenoble

CEA Code: SL-DRT-22-0574

Contact: niccolo.castellani@cea.fr

A new technological development consists in using CMOS at cryogenic temperatures after discovering that their performances highly improve. Possible applications are aerospace, high performance servers, quantum computing and data centers. Meanwhile, many emerging memory technologies were proposed as Flash replacement thanks to a reduced programming time, a better endurance and a CMOS compatible process flow. Nonetheless, emerging memories are sensitive to the increase of temperature that degrades their performances, getting very interesting to conduct a reliability study at cryogenic temperature. Various future applications might be concerned, like In-Memory Computing (IMC) and Artificial Intelligence (AI) that are proposed to overcome the Von Neumann bottleneck embedding computation and storage in the same device. The subject of this thesis is pioneering: literature is not developed, mostly lacking about statistical analysis. In this scenario, the LETI is a state-of-the-art research facility since diverse emerging memories are already developed and cryogenic probers are available. The student will initially drive a memory performances benchmark and then will focus on in-depth reliability analysis on the most promising technology.

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