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Co-design HW/SW for on-chip incremental learning

Technological challenge: Artificial intelligence & Data intelligence (learn more)

Department: Département Systèmes et Circuits Intégrés Numériques (LIST)

Laboratory: Laboratoire Intelligence Intégrée Multi-capteurs

Start Date: 01-09-2022

Location: Grenoble

CEA Code: SL-DRT-22-0377

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Current deep learning algorithms suffer, on the one hand from catastrophic forgetting preventing incremental learning, and on the other hand when implemented on silicon, limiting embedded applications especially when learning needs to be performed. This thesis subject therefore proposes to explore incremental learning algorithms on time series, inspired from bio- inspired algorithms existing in our laboratory on image databases. Indeed, the implementation of incremental learning will take on its full meaning when the environment is changing and therefore particularly with dynamic data. Keep in mind the goal of having the most energy efficiency on a hardware target. Secondly, it will be a question of evaluating the performance of these algorithms on the existing hardware platforms within the CEA / List and / or on new disruptive computing architectures to be imagined. For this, questions of partitioning algorithms on local CPU and / or on the accelerator part, quantification of data and operators, memory bandwidth on and off the chip will be addressed. This thesis can go as far as evaluating the advantages that the use of advanced technology could have (non-volatile memory, 3D, etc.) for a full system to Technology Co Optimization (STCO). The end goal will be to keep performance down by a factor of ten to one hundred compared to the state of the art.

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