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Self-adapting and reliable interconnect network for AI architectures

Technological challenge: New computing paradigms, circuits and technologies, incl. quantum (learn more)

Department: Département Systèmes et Circuits Intégrés Numériques (LIST)

Laboratory: Laboratoire Environnement de Conception et Architecture

Start Date: 01-09-2022

Location: Saclay

CEA Code: SL-DRT-22-0319

Contact: hana.krichene@cea.fr

Deep learning algorithms, such as Convolutional Neural Networks (CNN), are used for many applications as image recognition and/or classification. CNN are made up of several layers that generate significant movements of data. Many works have proposed architectures dedicated to the inference of CNN, but few have proposed optimizations for the interconnection network. The implementation of CNN must ensure high computational parallelism, but it must also optimize data movements to optimize energy efficiency. Additionally, the accelerators for CNN that are currently developed, are not optimized for applications with dynamic behavior causing irregular data transfers. Furthermore, technological evolutions are leading to a greater sensitivity of the architectures to environmental disturbances, in particular for communication that must be made more reliable. Such irregularities of the traffic, combined with the appearance of faults within the network, can lead to network congestion. In this context, load balancing and resource sizing become difficult tasks to anticipate in order to maintain a satisfactory quality of service for the application. This thesis proposes to address these issues aims to develop an intelligent NoC for AI architectures. A dynamic and fault-tolerant NoC will be proposed to support the implementation of evolving and flexible AI algorithms. It will be based on a management optimized for the non-regular traffic of data and for an energy-efficient implementation.

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