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Design of an Improved Memory System for Sparse Data Sets

Technological challenge: New computing paradigms, circuits and technologies, incl. quantum (learn more)

Department: Département Systèmes et Circuits Intégrés Numériques (LIST)

Laboratory: Laboratoire Systèmes-sur-puce et Technologies Avancées

Start Date: 01-09-2022

Location: Grenoble

CEA Code: SL-DRT-22-0304

Contact: adrian.evans@cea.fr

The performance of the processors used in scientific computing and for machine learning applications continues to improve. One of the primary techniques for achieving performance consists of exploiting parallelism; however, this approach works well only when the data is regular. Many real-world problems involve sparse data sets, making it difficult to fully exploit parallel hardware. Furthermore, transferring data from the memory sub-system to the processor is often the limiting factor for performance, due both to bandwidth and power constraints. For problems with sparse data, optimizing the memory accesses is more challenging as the access patterns are irregular. There is a need for new hardware support for sparse data, as demonstrated by emerging GPUs that are now providing such hardware solutions. In this thesis, the candidate will start by reviewing the state of the art in terms of memory and cache systems for high-performance processors, including an in-depth study of the vast literature on representations for sparse matrices and sparse data. The candidate will then propose new architectures for a memory sub-systems optimized for this class of problem, including analyzing the interactions with a conventional cache hierarchy. The solutions may involve direct hardware support for specific data-structures, data compression or other techniques. The architectures will first be evaluated using a light-weight prototype and the most promising ones will be implemented on an high-end FPGA, integrated with a RISC-V processor optimized for scientific computing. This thesis will take place in the LSTA laboratory of the CEA in Grenoble, a lab that has a strong background in computer science, the design of high-performance compute systems. The ideal candidate has experience in computer architecture, hardware design and, preferably some background in linear algebra and numerical analysis.

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