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Analyzing Interference Effects on Timing Predictability of Many-Core Architectures

Technological challenge: Cyber physical systems - sensors and actuators (learn more)

Department: Département Systèmes et Circuits Intégrés Numériques (LIST)

Laboratory: Laboratoire Environnement de Conception et Architecture

Start Date: 01-10-2022

Location: Saclay

CEA Code: SL-DRT-22-0276

Contact: oumaima.matoussi@cea.fr

An increasing number of safety-critical systems such as autonomous vehicles, aircraft flight control and medical devices are controlled by many-core processors interacting in real-time with their environment. Since the consequences of failure of such systems can lead to substantial damage, it is crucial to develop safety verification methods to minimize the risk of deficiency. A typical cause of such failure is timing problems. Therefore, computing safe and tight timing bounds is fundamental to the successful execution of these real-time systems. When multi-threaded safety-critical applications are deployed on such many-core systems, they may cause contention delays. This phenomenon is referred to as cross-core interference, which is usually defined as as a result of concurrent accesses to shared resources (e.g. RAM, caches, buffers and interconnect) of tasks running on different cores and that execute within overlapping time windows. Therefore, the software behavior contributes a large part of the interference delays and should be analyzed while taking into account the timing model of the underlying hardware. The objective of this PhD is to propose a formal and practical framework for interference quantification and mitigation. The main expected contributions consist of: - modeling hardware resources susceptible to interferences like caches, buffers and interconnect using a formal specification language and analysis of the generated timed traces to compute interference delay bounds - Applying profiling techniques or criticality analysis on the generated traces to smartly capture the critical interleavings of accesses to shared resources is crucial to ease the complexity of the analysis and ensure the scalability of the proposed approach. - devising software strategies, at the compiler level, to mitigate interferences and increase the predictability of the system. These strategies rely on the interference delay bounds resulting from trace analysis in order to instrument the compiler to efficiently schedule accesses to shared resources (i.e. minimize contention without compromising the performance of the system).

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