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PhD thesis- 3D Superconducting Interconnects for Quantum Applications

Technological challenge: New computing paradigms, circuits and technologies, incl. quantum (learn more)

Department: Département Composants Silicium (LETI)

Laboratory: Laboratoire Packaging et 3D

Start Date: 01-10-2022

Location: Grenoble

CEA Code: SL-DRT-22-0233

Contact: jean.charbonnier@cea.fr

As part of Quantum Silicon Grenoble project, teams at CEA-LETI, CEA-IRIG and Néel Institute aim at building a quantum accelerator with silicon spin quantum bits (qubits). Compatible with large-scale production, existing integration processes on Si are a real advantage for the scalability of these qubits. However, the extreme qubit operating conditions (cryogenic temperatures =1K, high frequencies in the range of a few GHz, high signal density) require the development of adapted technological building blocks as well as multi-chip module platforms, designed to bring control electronics circuits closer to the qubits in the cryostat. The integration of superconductors is promising to optimize the coupling between the qubits and their control electronics. Indeed, their vanishing resistance at low temperatures adds flexibility to the design and sizing of the interconnects (e.g. microbumps or routing tracks) located between the qubits and control electronics circuits. The low thermal conductivity of superconductors can be used to protect the qubits from the heat generated by the control electronics circuits integrated close-by. Finally, the low dispersion of superconductors favors high frequency signal transmission needed to encode and read the information stored in the qubits. This thesis will focus on the fabrication of superconducting interconnects and the study of their thermal properties. This will include the structural, morphological and electrical characterizations of superconducting films deposited in the CEA-LETI clean-room facilities and integrated in quantum structures as well as the establishment of low temperature compatible thermal conductivity measurement set-up, protocol and sample design. The goal will be to transfer the acquired knowledge in term of integration and thermal conductivities to develop the next generation of multi-chip platform hosting qubits and control electronics circuits. The PhD student will be part of the 3D integration and packaging lab of CEA-LETI (Grenoble) and will interact very closely with the Spectral-imaging laboratory for space science at CEA-IRFU (Saclay) for thermal conductivity measurements. The PhD student will carry experiments on both sites even if based at Grenoble.

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