Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Unifying Distributed Memories in Heterogeneous Systems

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-10-2018

SL-DRT-18-0290

loic.cudennec@cea.fr

Future computers in high-performance and embedded systems lead to complex memory hierarchies. Hundreds of computing nodes will have to be connected to tera-bytes of memories. In such systems, both the processing units (CPU, GPU, DSP, FPGA) and the memories (DRAM, NVRAM, FLASH) can be heterogeneous. Several architectures exist (distributed memory, shared memory, NUMA) with different hardware implementations (cache coherence, communication protocols), software implementations (thread parallelism, OpenMP, transactions) and communication technologies between processing units and memory (MPI, RDMA, RoCE, CCIX, GenZ). None of the approaches above offer a simple, unified programming model and memory model for parallel applications. The purpose of this Ph.D. Thesis is to study the possibility of using emerging technologies related to computing units, hybrid memories (persistent or not) and remote communication standards in order to accelerate data sharing onto heterogeneous platforms and provide a convenient programming model.

A quantum algorithm to compute classical Worst-Case Execution Time (WCET)

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-10-2018

SL-DRT-18-0365

sergiu.carpov@cea.fr

Worst Case Execution Time (WCET) are important data elements to feed any safety and schedulability analysis of safety critical real-time systems for which any default can jeopardize the life of the system or even threaten the life of human beings. WCET is particularly important in the context of real-time autonomous systems (e.g. robotics, self-driving cars). The problem of computing safe upper bonds of execution time is well known, but the challenge is also to have them tight to avoid over-engineering of real-time systems and mastering their costs. But this challenge is still not fully reached and moreover tends to pursue a moving target as the hardware and software architecture of real-time systems also moves forward (pipelines, cache memories, multi-cores, etc.). The goal of this PhD Thesis is to explore what quantum computing can do to simplify the problem, bring for more precision and capacity of analysis of these issues. This work will be supported by existing state of the art, and could explore a bit further than the strict domain of usual WCET analysis. Depending on the candidate profile, the subject will bend more towards either implementation aspects - How to best implement a WCET algorithm onto an available quantum simulator (eg. QX simulator, Quantum Learning Machine), or computational complexity theory aspects.

Integrated outphasing PA architecture and design for 5G

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Architectures Intégrées Radiofréquences

01-09-2018

SL-DRT-18-0453

alexandre.giry@cea.fr

Objective of the proposed thesis is to study advanced Outphasing PA (OPA) architectures and investigate opportunities for integration in RFSOI technology in order to propose high performance low cost solutions for future 5G applications. 5G will allow to address the continuously growing demand for connected objects as well as mobile communications with high data rates and instant access to information. The need for high linearity and reduced power consumption, make integrated Power Amplifier (PA) design for 5G applications highly critical. In addition, the trend towards higher data rates leads to RF signals with higher peak to average power ratio that make integrated PA design even more challenging. This calls for an important shift from traditional integrated PA architectures to advanced integrated PA architectures with high linear efficiency and output power. Objective of the proposed thesis is to study advanced Outphasing PA (OPA) architectures and investigate opportunities for integration in RFSOI technology in order to propose high performance low cost solutions for future 5G applications. The candidate will investigate different OPA architectures and perform a detailed study of the most promising architecture, proposing innovative ways to improve performances. He/she will investigate practical implementation in RFSOI technology, paying special attention to the performances and occupied silicon area. Integrated PAs will be fabricated on RFSOI technology and characterized, potential differences between simulated and measured performances will be analyzed and justified. Directives and perspectives for high performance integrated OPA design will be proposed.

Development of innovative piezoelectric micromachined ultrasound transducer (pMUT) for automotive applications

Département Composants Silicium (LETI)

Laboratoire Composants Micro-Capteurs

01-09-2018

SL-DRT-18-0471

bruno.fain@cea.fr

The potential use of piezoelectric micromachined ultrasound transducers (pMUT) within smartphones, tablets and connected devices have raised a growing interest during the last years to build new fingerprint sensors and achieve better, low-power range-finder. To meet the specific needs of these new applications, the performances of pMUT have to be increased. This Ph.D. thesis aims at building new devices to cope with the requirements of automobile applications. The conception, the fabrication and the characterization of the pMUT will be investigated by the Ph.D student. The conception will be based on both analytical approaches and finite elements modelling (ANSYS, Comsol Multiphysics). The fabrication process will be achieved within the 8 inches MEMS Platform of CEA-LETI with the strong support of the CEA teams. The characterization, mostly probe measurements at the wafer level, will confirm and refine the models. The relevance of the devices for the targeted applications will be evaluated. For this purpose, the Ph.D. student is expected to have strong background in mechanics. He will tackle both scientific and technological challenges. He should be an autonomous team player.

Analog to Digital Converter for Neural Network based Acoustic Detection System for IoT Systems

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Architectures Intégrées Radiofréquences

01-09-2018

SL-DRT-18-0494

dominique.morche@cea.fr

The purpose of this PhD is to develop a new analog to digital converter whose output will be some trains of spike. This waveform is particularly adapted to the neural network processing. A joint optimization between the ADC and the neural network will be done by the PhD. Signal Detection and Classification is becoming a key function in the internet of things to extract useful information from the environment. For such functionality, neural network based processing is becoming more and more interesting. However, the power efficiency is often limited by the analog to digital interface which is mandatory. Therefore, more power efficient analog to digital interface are required and their power consumption should adapt itself to the application requirements. That is the reason why, the purpose of this PhD is to develop a new analog to digital converter whose output will be some trains of spike. This waveform is particularly adapted to the neural network processing. A joint optimization between the ADC and the neural network will be done by the PhD, in collaboration with a Post-Doc who will be working on the digital part. The design will exploit the 28nm FD-SOI technology developed by STMicroelectronics. Several circuit will be design, fabricated and tested. The objective at the end is to build a demonstrator able to distinguish audio signals. Industrials use cases will be considered. The Phd will be done in collaboration with IMT Atlantique. The PhD will be asked to present his work in the scope of collaborative European project.

Adaptive CMOS Image Sensor for vision systems

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Circuits Intégrés, Intelligents pour l'Image

01-01-2018

SL-DRT-18-0507

gilles.sicard@cea.fr

The aim of this thesis is to explore new kind of smart vision sensor architectures using for enhance the sensor reactivity and for simplify the image processing. The studied vision system will use new 3D microelectronic technologies from CEA-leti to perform both an image acquisition and a real time local adaptation to optimize the pixel setup to its using environment. The PhD student will benefit during his 3-years thesis of the expertise and the scientific excellence of the CEA leti to attend objectives with a high level of innovation through international patents and publications. These technologies are capable to stack several integrated circuits. The main advantage is to propose a high density of interconnections between them, allowing connection at the pixel level. The aim of the adaptive system is to control the pixel (or group of pixels) setup to optimize its functioning and regularize the output image. The dynamic and autonomous candidate, will have a microelectronic master degree, specialized in analog integrated circuit design. A good knowledge of circuit design CAD tools will be important (Cadence, and also Matlab) and good knowledge in image processing will be appreciated. This thesis will start with the state of the art study, then the PhD student will define the optimal architecture. Finally, a test chip will be designed and tested. It will demonstrate the scientific and industrial potentialities of the proposed solutions.

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