Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Exploration and design of in-memory computing architectures based on emerging non volatile memories

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Silicium des Architectures Numériques

01-09-2018

SL-DRT-18-0258

jean-philippe.noel@cea.fr

The thesis objective is to study and propose new architectures for in-memory-computing based on emerging non-volatile mémories and thus explore future applications. L'objectif de cette thèse est d'explorer l'utilisation des mémoire non-volatiles émergentes pour les architectures de in-memory-computing afin d'ouvrir le champ d'application de ces mémoires limitées aujourdh'ui à des implemntations SRAM. The usage of any devices, from embedded to super-computers, is becoming more and more data-centric. On the other hand, the performance gap between processor and memory has been steadily growing during the last decades (known as the ?memory wall?). The energy consumption gap between computation (GFlop/s) and data-movement (GByte/s) is also showing the same trend. A very large proportion, if not the largest, of the efforts made by silicon companies and researchers have been focused on improving the characteristics of memories such as size, bandwidth, non-volatility, etc. The solution advocated to reduce the data-movement cost amounted to bring part of the memory (e.g. the caches) on the die nearby the processor. Despite the clear advantages of cache hierarchy, the latency of data transfers between the different memory levels remains an important performance bottleneck. In terms of energy consumption, I/O largely dominates the overall cost (70% to 90%). Eventually, in terms of security, data transfers between CPU and memory constitutes the Achilles heel of a computing system largely exploited by hackers. Therefore, other solutions came up over the years to address those problems. They can be grouped in the following terms: Processing-In-Memory, Logic-In-Memory and In-Memory-Computing (or Computing-In-Memory). Processing-In-Memory (PIM) is a concept based on DRAM process consisting in driving computation units implemented in DIMMs through the existing memory bus. In more recent works, and with the progress of the 3D technologies, researchers propose to design stacks of computation unit next to the DRAM stack, which permits to create massive data parallelism. Logic-In-Memory is the concept of integrating some computation ability into the memory. However, it is more used to implement logic operations on a specific memory layer or logic layer dedicated for 3Ds memories. Finally, In-Memory-Computing (IMC) consists in integrating a part of the computation units into the memory boundary, which means that data do not leave memory. This should offer significant gain in the execution time, reducing the power consumption and improving the security. The IMC concept has been successfully implemented in CEA-LETI. Despite the promising results of existing works, all the applications has been experimented only based on SRAM bitcell arrays. To go further and target high capacity memory application (video, ...), the usage of non-volatile memories based on emerging technologies (ReRAM, PCM, MRAM, ...) will be explored in this thesis. Based on in-house software platform and hardware architecture, the main goal will be to evaluate the performance (power, timing, ...) and explore new architecture and design solutions.

Unifying Distributed Memories in Heterogeneous Systems

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-10-2018

SL-DRT-18-0290

loic.cudennec@cea.fr

Future computers in high-performance and embedded systems lead to complex memory hierarchies. Hundreds of computing nodes will have to be connected to tera-bytes of memories. In such systems, both the processing units (CPU, GPU, DSP, FPGA) and the memories (DRAM, NVRAM, FLASH) can be heterogeneous. Several architectures exist (distributed memory, shared memory, NUMA) with different hardware implementations (cache coherence, communication protocols), software implementations (thread parallelism, OpenMP, transactions) and communication technologies between processing units and memory (MPI, RDMA, RoCE, CCIX, GenZ). None of the approaches above offer a simple, unified programming model and memory model for parallel applications. The purpose of this Ph.D. Thesis is to study the possibility of using emerging technologies related to computing units, hybrid memories (persistent or not) and remote communication standards in order to accelerate data sharing onto heterogeneous platforms and provide a convenient programming model.

Refrigerant purification in absorption chiller by heat and mass transfer optimization in falling films inside rectifier and generator

Département Thermique Biomasse et Hydrogène (LITEN)

Laboratoire Systèmes Solaires Haute Température

01-10-2018

SL-DRT-18-0308

francois.boudehenn@cea.fr

From more than fifteen years, the development of air-conditioning offers more and more comfort to people. Major part of commercial air-conditioners uses electricity-powered vapor compression machines to provide the frigorific effect. The use of that technology must face to a paradox: more the number of air-conditioners installed in a city increases, more heat released to urban atmosphere rises, thus increasing the ambient air temperature which implies a decreasing the performance of the chiller and increasing the cooling load of buildings. In fine, peak electricity demand for cooling can be tripled. One of the solution could be the use of thermally driven chillers powered by waste-heat or solar energy. Ammonia-water chillers are particularly interesting because of their low production and maintenance costs. The main failing of this working pair is the small difference of volatility between the absorbent and the refrigerant, which implies the use of a rectifier to remove traces of water in the ammonia vapors at the outlet of the generator. In this context, the thesis will focus on understanding and modeling of coupled heat and mass transfers at the steam generation part (generator/rectifier) made by falling film. An experimental validation will be realized using an existing prototype at laboratory. This experimental and numerical validation will then make possible a global steam generation optimization aimed at improving overall compactness and increasing the performance of the thermodynamic cycle.

Bio-inspired vision chain for scene analysis.

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Adéquation Algorithmes Architecture

01-10-2018

SL-DRT-18-0309

laurent.soulier@cea.fr

Artificial vision systems (camera(s) and processor(s)) have recognition capabilities well below those achieved by biological systems (eye - cortex). Moreover, biological systems are able to process information within a few milliseconds, which is still out of range of electronic systems, even though their electronic image sensors are far from achieving the resolution of human eyes (few dozen megapixel against more than one hundred million). This thesis aims at addressing the challenge posed by the biology by designing integrated bio-inspired sensor architectures. Our approach is based three assumptions: first, resolution biological imaging sensors is not uniform, the best resolved zone (the fovea) is dedicated to the acquisition of the areas of interest of the scene; secondly, pre-processing from the sensor are used to compress the information; finally, the processing of information is context and prior knowledge dependent. This exploratory thesis, aims to devise, within the frame of these hypothesis, breakthrough solutions with respect to the state of the art, to endow autonomous artificial systems (drones of all kinds (UAV, UGV, ...), machine tools, smart camera) of ability to perception of their complex environment, while using only limited resources, i.e. those of embedded systems. The candidate should have strong tastes or skills in image processing and digital architectures.

Automatic generation of scalable and energy efficient neuronal processor

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-10-2018

SL-DRT-18-0315

thomas.peyret@cea.fr

Neuronal networks are more and more used for everyday applications (e.g. face recognition, image labeling) as well as critical ones such as in automotive field with pedestrians and obstacles detection. Using neuronal networks in an embedded system is challenging and need high energy efficiency computing resources for neuronal network execution. CEA has developed a programmable processor ?PNeuro? able to accelerate the execution of a neuronal application with a very high energy efficiency. However, in its current version, it is not able to run neuronal network with a large number of layers. The main idea of the thesis is to leverage on this processor to generate scalable neuronal network programmable accelerator for different size of network. Especially, this architecture should be able to execute bigger networks, but also allow network cascading and/or parallel execution. The generated architecture can be seen as a CGRA (Coarse Grain Reconfigurable Architecture) dedicated for neuronal network applications. This thesis work will firstly tackle the well-known ?memory wall? problem for such an architecture, but also ensure the programmability. Safety issues could also be considered. The Ph.D. student will propose innovative ways to automatically generate such an architecture with scalable data access, parallelism management and programmability.

A quantum algorithm to compute classical Worst-Case Execution Time (WCET)

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-10-2018

SL-DRT-18-0365

sergiu.carpov@cea.fr

Worst Case Execution Time (WCET) are important data elements to feed any safety and schedulability analysis of safety critical real-time systems for which any default can jeopardize the life of the system or even threaten the life of human beings. WCET is particularly important in the context of real-time autonomous systems (e.g. robotics, self-driving cars). The problem of computing safe upper bonds of execution time is well known, but the challenge is also to have them tight to avoid over-engineering of real-time systems and mastering their costs. But this challenge is still not fully reached and moreover tends to pursue a moving target as the hardware and software architecture of real-time systems also moves forward (pipelines, cache memories, multi-cores, etc.). The goal of this PhD Thesis is to explore what quantum computing can do to simplify the problem, bring for more precision and capacity of analysis of these issues. This work will be supported by existing state of the art, and could explore a bit further than the strict domain of usual WCET analysis. Depending on the candidate profile, the subject will bend more towards either implementation aspects - How to best implement a WCET algorithm onto an available quantum simulator (eg. QX simulator, Quantum Learning Machine), or computational complexity theory aspects.

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