Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PostDocs : selection by topics

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Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-01-2020

PsD-DRT-20-0029

francois.andrieu@cea.fr

For integrated circuits to be able to leverage the future ?data deluge? coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this ?memory wall? consists in processing the information in-situ, owing to In-Memory-Computing (IMC). However, today's existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory. The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.

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Electronic properties of van der Waals layered GeSbTe superlattices for innovative resistive interfacial Phase-Change Memories (iPCM)

Département des Plateformes Technologiques (LETI)

Laboratoire

01-02-2020

PsD-DRT-20-0031

pierre.noe@cea.fr

Resistive Phase-Change Memories (PCMs) are the best candidates in order to replace Flash memories, realization of storage class memories (SCMs) as well as neuromorphic applications. Nevertheless, PCMs exhibit certain limits hindering their wide use as non-volatile memory in the next future. The replacement of the bulk GeSbTe PCM by van der Waals layered GeSbTe superlattices in iPCMs (interfacial PCMs)is a very promising solution. Although the superior performance of iPCMs is well established, the origin of the resistive transition mechanism upon application of electric pulses remains unclear. This is mainly due to the lack of a robust description of their structure. Recently, we have been able to give a first description at the atomic scale (P. Kowalczyk et al., Small, 14, 24, 1704514, 2018). However, there is still a lot of work to understand and control the atomic structure regarding the electronic properties in order to finally evidence the physical mechanism behind the resistive transition in iPCMs. In that context, the work of this post-doctorate will consist of supporting the LETI's iPCMs team (material / physics, microelectronic devices, simulations) by performing and manging the analysis of the electronic transport properties of prototypical iPCM systems in thin film layers as well as afetr integration into state of the art memory devices. This will involve the realization and/or participation in electrical measurements (resistivity, Hall, iPCMs memories ...) and nanocharacterization of prototypical iPCMs stacks (XRD, STEM-HAADF, Raman / FTIR ...) on the Nanocharacterization platform of CEA Grenoble (PFNC). All this will then serve as a basis for AIMD simulations of the impact of an electric field on such vdW GeSbTe structures in order to be able for the first time to highlight the origin of the electronic transition in iPCMs devices.

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Nano-optomechanical silicon accelerometer for high performance applications

Département Composants Silicium (LETI)

Laboratoire Composants Micro-Capteurs

01-06-2020

PsD-DRT-20-0035

sebastien.hentz@cea.fr

Inertial sensors (accelerometers and gyrometers) are at the heart of a large number of consumer-and low-cost applications such as smartphones and tablets, but also higher added value, higher-performance applications such as navigation for autonomous vehicles, aeronautics or space. Silicon microsystems (MEMS) are today a very mature technology and several millions are sold each year. However, they are today unable to address high-performance applications. LETI has been pioneering the development of optomechanical sensors "on-chip": light is guided in thin silicon layers in a similar way to photonics techniques. This light interacts with an object in motion such as a mechanical resonator or a seismic mass. This displacement modulates the intensity of the measured light, which allows the determination of the object's acceleration. This technology was developed in the 2000s in fundamental research, and in particular enabled gravitational wave detectors. LETI is developing this technology on-chip at the nanoscale, with displacement sensitivities several orders of magnitude better than electrical transductions. First optomechanical accelerometers were designed and fabricated in LETI's quasi-industrial clean rooms for initial characterization tests. The hired fellow with have to become familiar with these devices, to confirm the first optical results, and then most importantly to assess their performances under acceleration: a test setup will have to be realized for this purpose. She or he will have to provide feedback on the modeling and the design from the measurements in order to ensure the comprehension of all phenomena at play. Finally, the postdoctoral fellow will have to propose new designs aimed at the expected high performances. These devices will be fabricated by the clean room, tested by the fellow and and compared to the expected performance.

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Inductors for quantum reflectometry

Département Composants Silicium (LETI)

Laboratoire Composants Radiofréquences

01-04-2020

PsD-DRT-20-0039

jean-philippe.michel@cea.fr

Quantum computing is nowadays a strong field of research at CEA-LETI and in numerous institutes and companies around the world. Reflectometry is one of the major avenues envisaged for Qubits reading. Reflectometry and frequency multiplexing techniques requires many small resonators that must be positioned as close to the quantum chip as possible. First demonstrations performed with discrete inductors showed limitations in terms of size and coupling. Large-scale passives component integration technologies mastered at CEA-LETI can meet these dimensional constraints. Especially, CEA-LETI is positioned at the highest level of the state of the art in magnetic inductors on silicon, with record inductance densities (> 3 000 nH/mm˛). First measurements have already validated the operation of the technology at very low temperature. We now have to demonstrate the feasibility of an inductive interposer dedicated to Qubits reading by leveraging high inductance densities. The student will perform the accurate RF characterization of our magnetic inductors at cryogenic temperature. He will analyze the obtained results to describe the electrical and magnetic behaviour of the components. The bibliographic analysis and the studies already carried out will enable him to define a new technological stack combining the advantages of magnetic materials and superconductors. He will propose suitable designs to realize high quality factor inductors and an inductive interposer for Quantum reflectometry.

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Modeling of trapping and vertical leakage effects in GaN epitaxial substrates on Si

Département Composants Silicium (LETI)

Laboratoire de Simulation et Modélisation

PsD-DRT-20-0043

marie-anne.jaud@cea.fr

State of the art: Understanding and modeling vertical leakage currents and trapping effects in GaN substrates on Si are among the crucial subjects of studies aimed at improving the properties of GaN power components : current collapse and Vth instabilities reductions, reduction of the leakage current in the OFF state. Many universities [Longobardi et al. ISPSD 2017 / Uren et al. IEEE TED 2018 / Lu et al. IEEE TED 2018] and industrials [Moens et al. ISPSD 2017] are trying to model vertical leakages but until now, no clear mechanism has emerged from this work to model them correctly over the entire range of voltage and temperatures targeted. In addition, modeling the effects of traps in the epitaxy is necessary for the establishment of a a robust and predictive TCAD model of device. For LETI, the strategic interest of such a work is twofold: 1) Understanding and reducing the effects of traps in the epitaxy impacting the functioning of GaN devices on Si (current collapse, Vth instabilities?) 2) Reaching the leakage specifications @ 650V necessary for industrial applications. The candidate will have to take charge in parallel of the electrical characterizations and the development of TCAD models: A) Advanced electrical characterizations (I (V), I (t), substrate ramping, C (V)) as a function of temperature and illumination on epitaxial substrates or directly on finite components (HEMT, Diodes, TLM ) B) Establishment of a robust TCAD model integrating the different layers of the epitaxy in order to understand the effects of device instabilities (dynamic Vth, dynamic Ron, BTI) C) Modeling of vertical conduction in epitaxy with the aim of reducing leakage currents at 650V Finally, the candidate must be proactive in improving the different parts of the substrate

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Low temperature process modules for 3d coolcube integration : through the end of roadmap

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-03-2019

PsD-DRT-19-0048

claire.fenouillet-beranger@cea.fr

3D sequential integration is envisaged as a possible solution until the end of CMOS roadmap. Different process modules have been developped @ 500°C for planar FDSOI technology in a gate first process. However, regarding bottom transistor level stability in CoolcubeTM integration, and yield consideration, the need to reduce further the top transistor temperature down to 450°C should be explored. The post-doc will have in charge the development of specific technological modules at low temperature both 500°C and 450°C for FDSOI planar devices to acquire a solid knowledge in low temperature CMOS process integration. The specific low temperature gate module will be addressed on planar devices. The threshold voltage modulation will also be studied. The work will be performed in collaboration with the technological platform process of LETI for the low temperature modules development. The electrical characterization in collaboration with the characterization laboratory and the TCAD simulations team of LETI.

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