Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PostDocs : selection by topics

Simulation of semimetal nanowires

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-11-2017

PsD-DRT-18-0004

jean-pierre.colinge@cea.fr

The candidate's mission will be: ? Simulation using ab-initio tools of the structure of bismuth nanowire bands of different diameters (from 1 nm to 10 nm). ? Extraction of parameters as effective masses, density of states, band offsets for these nanowires. ? Implementation of these parameters in a NEGF simulator to simulate bismuth nanowire transistors with variable diameter. ? Ab-initio simulation of the bismuth-dielectric nanowire interface and study of various elements of chemical passivation. ? This work will be done in collaboration with LETI / DCOS / SCME / LSIM (Philippe Blaise) ? The candidate will interact with an experimental team that will produce the simulated devices and will help to supervise one or more doctoral students, in collaboration with IMEP. ? The candidate will interact with the LTM to help predict the properties of the grid bismuth-insulator interface and implement the IMEP results in the simulator.

Design for reliability for digital circuits

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Fiabilité et Intégration Capteur

01-03-2018

PsD-DRT-18-0010

valentin.gherman@cea.fr

Flash memories are a key enabler for high-temperature applications such as data acquisition and engine control in aerospace, automotive and drilling industries. Unfortunately, the retention time of flash memories is very sensitive to high temperatures. Even at relatively moderated temperatures, flash memories may be affected by retention-related problems especially if they are set to store more than one bit per cell. This impact can be mitigated by periodically refreshing the stored data. The problem is that, in the presence of a variable operating temperature that could be due to variable environmental and workload conditions, a fixed data-refresh frequency may become disproportionately large with a subsequent impact on response time and cycling endurance. The first objective of this project is to implement a data-refresh method based on a specially designed counter that is able to (a) track the evolution of the temperature and its impact on the data retention time of Flash memory blocks, (b) trigger warnings against potential retention time hazards and (c) provide timestamps. The second objective is to find the distribution law that gives the evolution of the number of data retention errors in time. The goal is to implement a methodology able to infer the remaining retention time of flash memory pages based on their data retention age, i.e., the elapsed time since data was stored, and the number of retention and non-retention errors. The publication of the scientific results in high-ranked conferences and journals is major project objective.

Compressed Sensing Electron Tomography: Quantitative Multi-dimensional Characterization of Nanomaterials

Département Technologies Silicium (LETI)

Autre laboratoire

01-01-2019

PsD-DRT-19-0015

zineb.saghi@cea.fr

Electron tomography (ET) is a well-established technique for the 3D morphological characterization at the nanoscale. ET applied to spectroscopic modes for 3D structural and chemical analysis has become a hot topic but necessitates long exposure times and high beam currents. In this project, we will explore advanced compressed sensing (CS) approaches in order to improve the resolution of spectroscopic ET and reduce significantly the dose. More precisely, we will focus on the following two tasks: 1. Comparison of total variation minimization, orthogonal or undecimated wavelets, 3D curvelets or ridgelets and shearlets for nano-objects with different structures/textures; 2. Comparison of PCA and novel CS-inspired methods such as sparse PCA for dimensionality reduction and spectral un-mixing. The code will be written in Python, using Hyperspy (hyperspy.org) and PySAP (https://github.com/CEA-COSMIC/pysap) libraries. The project follows a multidisciplinary approach that involves the strong expertise of the coordinator in ET and the input of two collaborators with complementary skills: Philippe Ciuciu with expertise in MRI (DRF/Joliot/NEUROSPIN/Parietal) and Jean-Luc Starck with expertise in cosmology, signal processing and applied maths (DRF/IRFU/DAP/CosmoStat). The three communities share a strong interest in compressed sensing algorithms.

Strain engineering on AlN thin films

Département Technologies Silicium (LETI)

Laboratoire

01-01-2019

PsD-DRT-19-0023

pierre.montmeat@cea.fr

AlN is one of the prime material due to its outstanding piezoelectric properties for many RF and MEMS applications. The performances of the devices strongly depend on the piezoelectric properties of the material and one promissing way to tune the properties is to set a mechanical strain to the AlN. The goal of the post-doctoral position is to strain AlN thin film by transferring them onto various substrates. In the case of flexible polymer substrate, the strain of the polymer can stress AlN. LETI has ever developed a process dedicated to the transfer of very thin silicon film onto a flexible substrate. the student will be in charge of : 1/ the transfer of AlN thin onto various substrates 2/ The mechanical and electrical characterization of the transfered films

Charge to spin conversion in HgTe topological insulators

Département d'Optronique (LETI)

Laboratoire des Matériaux pour la photonique

01-01-2018

PsD-DRT-18-0025

philippe.ballet@cea.fr

The intrinsic spin-momentum locking of Dirac fermions at the surface or interface of topological insulators opens the path towards novel spintronic effects and applications. Strained HgTe/CdTe is a model topological insulator and a very good candidate to design and demonstrate new spintronic devices exploiting the very large charge to spin conversion efficiency expected for such 2D systems. This postdoc position aims at realizing the first demonstration of the direct charge to spin conversion in topological HgTe nanostructures and use this demonstration as a building block for spin based logic elements.

Ultra Low Power RF Communication Circuit and System Design for Wake-Up Radio

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Architectures Intégrées Radiofréquences

01-01-2019

PsD-DRT-19-0026

dominique.morche@cea.fr

Today, there is a strong demand in developing new autonomous Wake-Up radio systems with tunable performances and independent clocking system. The objectives of the proposed contract it to exploit the capacity of CMOS FD-SOI technologies to develop such devices, improving power consumption and RF performance above the state of the art, thanks to the natural low parasitic and tuning capacity through back biasing of the FD-SOI . A particular attention will be paid to the development of a new power efficient, fast settling, frequency synthesis system. The chosen candidate will be involved both in RF system and circuit design, with the support of the experienced RF System & Design team.

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