Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PostDocs : selection by topics

Simulation of semimetal nanowires

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-11-2017

PsD-DRT-18-0004

jean-pierre.colinge@cea.fr

The candidate's mission will be: ? Simulation using ab-initio tools of the structure of bismuth nanowire bands of different diameters (from 1 nm to 10 nm). ? Extraction of parameters as effective masses, density of states, band offsets for these nanowires. ? Implementation of these parameters in a NEGF simulator to simulate bismuth nanowire transistors with variable diameter. ? Ab-initio simulation of the bismuth-dielectric nanowire interface and study of various elements of chemical passivation. ? This work will be done in collaboration with LETI / DCOS / SCME / LSIM (Philippe Blaise) ? The candidate will interact with an experimental team that will produce the simulated devices and will help to supervise one or more doctoral students, in collaboration with IMEP. ? The candidate will interact with the LTM to help predict the properties of the grid bismuth-insulator interface and implement the IMEP results in the simulator.

Data integration for the management of uncertainty in a simulation process

Département Imagerie Simulation pour le Contrôle (LIST)

Laboratoire Simulation et Modélisation en Electro-magnétisme

01-12-2017

PsD-DRT-18-0007

christophe.reboud@cea.fr

In the field of NonDestructive Testing (NDT), Probability of detection (POD) and false alarm rate are key quantities used to quantify the performance of a particular inspection setup. Simulation can be used to estimate such quantities, through a propagation of inputs uncertainty in the physical model. The CIVA platform developed at CEA LIST is recognized as a software of reference in the community for the simulation of NDT techniques. Firstly, the project aims at enhancing the description of inputs uncertainty, which is today somewhat arbitrarily described based on experts' judgement. Secondly, it aims at designing a model calibration strategy able to correct discrepancies between theory and practice, coming from phenomena that are not taken into account by the model. Among those effects, one can cite perturbations due to the environment or human factors, for instance. To reach these two goals, the method proposed consists in integrating experimental data to the simulation process. The work will be conducted in close collaboration with the LGLS laboratory of CEA's Directon de l'Energie Nucléaire (DEN), specialized in statistical modelling and developing the URANIE platform dedicated to sensitivity analysis and uncertainty quantification.

Design for reliability for digital circuits

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Fiabilité et Intégration Capteur

01-03-2018

PsD-DRT-18-0010

valentin.gherman@cea.fr

Flash memories are a key enabler for high-temperature applications such as data acquisition and engine control in aerospace, automotive and drilling industries. Unfortunately, the retention time of flash memories is very sensitive to high temperatures. Even at relatively moderated temperatures, flash memories may be affected by retention-related problems especially if they are set to store more than one bit per cell. This impact can be mitigated by periodically refreshing the stored data. The problem is that, in the presence of a variable operating temperature that could be due to variable environmental and workload conditions, a fixed data-refresh frequency may become disproportionately large with a subsequent impact on response time and cycling endurance. The first objective of this project is to implement a data-refresh method based on a specially designed counter that is able to (a) track the evolution of the temperature and its impact on the data retention time of Flash memory blocks, (b) trigger warnings against potential retention time hazards and (c) provide timestamps. The second objective is to find the distribution law that gives the evolution of the number of data retention errors in time. The goal is to implement a methodology able to infer the remaining retention time of flash memory pages based on their data retention age, i.e., the elapsed time since data was stored, and the number of retention and non-retention errors. The publication of the scientific results in high-ranked conferences and journals is major project objective.

Frequency tunable elastic plate wave resonators and filters

Département Composants Silicium (LETI)

Laboratoire Composants Radiofréquences

01-03-2017

PsD-DRT-17-0011

alexandre.reinhardt@cea.fr

The increasing number of frequency bands having to be dealt with in mobile phone systems require a huge number of band pass filters in such systems. In this context, the capability to provide frequency tunable resonators and filters is seen as a key enabling element in future wireless transmission systems. CEA-LETI has been working for more than 10 years on the development of resonators and filters exploiting the propagation of guided elastic waves in piezoelectric thin films. It has also proposed several concepts for frequency agile resonators and filters. The purpose of this post-doc will be to further develop these ideas and to apply them to the design of demonstrators matching realistic specifications. In collaboration with the other member of the project team, more focused on fabrication in clean rooms, the candidate will propose innovative structures demonstrating frequency tuning of reconfigurability, and will take in charge their electrical characterization.

Design / Technology Co-Optimization of SRAM and standard cells on stacked nanowires at the 5nm technology node

Archive des laboratoires DRT (ne pas utiliser)

Laboratoire Dispositifs Innovants

01-02-2017

PsD-DRT-17-0013

francois.andrieu@cea.fr

The post-doctoral position will focus on the layout of SRAM and standard cells dedicated to the 5nm node on stacked nanowires integrating a Direct Self-Assembly solution (DSA). He/she will use the SPICE model developed at LETI and interact with both model and process/integration teams to find the best layout for a set of cells.

Optimisation of the monolithic cascode device based on GaN/Si MOS-Channel HEMT technology

Département Composants Silicium (LETI)

Laboratoire Composants Electroniques pour l'Energie

01-02-2017

PsD-DRT-17-0017

erwan.morvan@cea.fr

In order to adress the requirements of power conversion in the field of electrical vehicule or photovoltaics, high performance GaN on Silicon power devices need to be developped. Such power devices must fulfill agressive specifications in terms of threshold voltage (> 2V), nominal current (100-200A), breakdown voltage (650 and 1200V) and stability (low "current collapse", low hysteresis). Discrete cascode configuration, consisting in a combination of a low voltage E-mode Silicon die and a hihg voltage D-mode GaN/Si die in a single package, has been developped by different laboratories and companies to adress this need (Transphorm, On-Semi, NXP, IR?). However, this approach has some drawbacks like parasitic inductances, device pairing, need of additionnal protection devices, cost, temperature limitation due to the Si die... The monolithic cascode is a very compact version of the cascode configuration that will allow to avoid those problems but also to improve the performance of E-mode devices developped at Leti (MOS-channel HEMT). Indeed, some actors in the field of GaN power devices already use this configuration with another E-mode technology (p-GaN gate). Monolithic cascode device has been demonstrated recently by CEA-Leti in the frame of a PhD thesis (2014-2016) on the basis of the 200mm GaN/Si, CMOS compatible, MOS-channel HEMT technology. The aim of this post-doc is to optimize the monolithic cascode structure in terms of On-state resistance, Figure Of Merit, switching losses and high switching frequency capability in order to meet the specifications of our industrial partners.

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