Scientific direction Development of key enabling technologies
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PhD : selection by topics

Technological challenges >> New computing paradigms, circuits and technologies, incl. quantum
8 proposition(s).

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Single address space for massively parallel computers

Département Systèmes et Circuits Intégrés Numériques

Laboratoire Systèmes-sur-puce et Technologies Avancées

01-09-2021

SL-DRT-21-0248

christian.fabre1@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

The generalization of a hierarchical organization of HPC machines into nodes of several dozen computing cores interconnected by a high-performance communication network has fragmented operating systems and greatly complicated the writing of applications. The proposal of a 128 bit processor architecture by the RISC-V community offers the possibility of reinterpreting the fundamental concepts in view of these fundamental changes in the structure of the machines. In particular, this proposal offers the opportunity to rethink memory addressing at the scale of the entire machine, and not locally at the level of each node. The purpose of this thesis will be to study the opportunities thus offered, to propose strategies for managing a 128-bit addressing space on the scale of the machine, and to evaluate its technical feasibility, hardware and software and expected performance. The Research Director for the PhD student will be Prof. Frédéric Pétrot, from Grenoble-INP/ENSIMAG. Christian Fabre (software) & Cesar Fuguet Tortorelo (hardware) from CEA LIST, will supervise the day-to-day work.

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Scaling evaluation of ultra-low power BEOL integrated HfO2-based ferroelectric memory arrays towards 28nm node

Département Composants Silicium (LETI)

Laboratoire de Composants Mémoires

01-10-2021

SL-DRT-21-0362

laurent.grenouillet@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

The recent discovery of ferroelectricity in HfO2 thin films generates a strong interest in integrating this CMOS-compatible and scalable material in ultra-low power ferroelectric memories and neuromorphic circuits. Within the last 6 months excellent results were reported on HfO2-based ferroelectric capacitors integrated in the Back-End Of Line of 130nm CMOS, confirming their potential for non-volatile memory applications. In this context, HfO2-based ferroelectric capacitors will be fabricated and electrically characterized to assess their potential to be scaled towards 28nm node. The candidate will perform advanced electrical characterization on state-of-the-art TiN/doped HfO2/TiN single capacitors with different areas, as well as 16kbit FeRAM arrays. Remanent polarization, coercive field, and imprint values will be extracted as a function of cycling (endurance) and temperature (data retention) for various pulse voltages/durations. Based on array characterization where large statistics is available, the physical mechanisms responsible for the reliability issues will be investigated. The results will be used to optimize the capacitor electrical properties to further design low voltage, ultra fast, scaled FeRAM memory arrays integrated within 28nm FDSOI node.

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Superconductor Integration for thermal management of quantum computing and spatial multi-chip platforms

Département Composants Silicium (LETI)

Laboratoire Packaging et 3D

01-09-2021

SL-DRT-21-0411

jean.charbonnier@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

As part of Quantum Silicon Grenoble project, teams at CEA-LETI, CEA-IRIG and Néel Institute aim at building a quantum accelerator with silicon spin quantum bits (qubits). Compatible with large-scale production, existing integration processes on Si are a real advantage for the scalability of these qubits. The extreme qubit operating conditions (cryogenic temperatures =1K, high frequencies in the range of a few GHz, high signal density) require the development of adapted technological building blocks. To interconnect the qubits and the controlled circuits, integration of superconducting metals is promising. Indeed, their vanishing resistance at low temperatures and the low thermal conductivity of superconductors also enables to protect the qubits from the heat generated by the control electronics circuits integrated close-by. Note that these developments will also benefit spatial applications sharing similar operating constraints. The thesis will focus on: 1) Studying the superconducting properties of Nb, NbN, TiN, Al and any combination of these materials during integration processes to optimize them for a single level of routing and multilayers pads. Establishing low temperature compatible thermal conductivity measurement set-up, protocol and sample design. 2) Transferring the acquired knowledge in term of integration and thermal conductivities to develop the next generation of multi-chip platform hosting qubits and control electronics circuits. The PhD student will be part of the 3D integration and packaging lab of CEA-LETI (Grenoble) and will interact very closely with the Spectral-imaging laboratory for space science at CEA-IRFU (Saclay) for thermal conductivity measurements.

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DC and RF advanced electrical characterization of passive and active components on 28nm-FDSOI at cryogenic temperatures

Département Composants Silicium (LETI)

Laboratoire de Caractérisation et Test Electrique

01-10-2021

SL-DRT-21-0504

mikael.casse@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

FDSOI technology appears as an option of choice for the design of circuits operating at low temperature (down to 4.2K and below), thanks to its high electrical performance, low variability, and the tunability of the threshold voltage offered by the application of a back bias under the BOX. In particular in the emerging field of the quantum computer, the control and the reading of quantum bits (qubits) require circuits operating as close as possible to these qubits, ideally at 4.2K and below, in particular in order to reduce the number of connections coming out of the cryostats. The interest of electronics operating at low temperature is however not limited to the development of the quantum computer, but is emerging for more and more applications (high energy physics, space, high performance computing, etc.), in a temperature range between 77K and a few mK. For efficient and reliable circuit design, it is essential to have compact models for digital, analog and RF applications in a design kit to predict MOSFET performance and power dissipation at these cryogenic temperatures. No compact model exists to date for this range of low to very low temperatures, forcing designers to ?blind? design their circuit. In addition, little work has been published so far on the performance evaluation and RF characterization of 28nm FDSOI technology at 77K or 4.2K. The objective of the thesis will be to work on the experimental setup of RF measurements down to 4.2K, as well as on the RF and DC characterization and the corresponding modeling of the 28nm-FDSOI technology for cryogenic operation.

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In-memory computing for sporadic applications in extreme environment

Département Systèmes et Circuits Intégrés Numériques

Laboratoire Fonctions Innovantes pour circuits Mixtes

01-10-2020

SL-DRT-21-0529

jean-frederic.christmann@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

In the context of Internet of Thins, applications are mainly sporadic and operating conditions such as the energy budget might be extreme. Power consumption reduction allows to improve the lifetime of embedded platforms or to integrate enhanced features. This PhD subject thus tackles the design of a memory component which would be able to compute complex calculations directly within the memory. This would highly reduce data exchanges with the processor and reduce the associated power consumption. The computing memory component will be designed using asynchronous logic, which provides a natural solution for IoT applications and brings strong physical implementation opportunities to further reduce the power consumption. Architecture development, validation though digital simulations, physical implementation and characterization of the component's performances are the main steps of the PhD contributions. Fabricating a chip which integrates the proposed ideas would allow to demonstrate the quality of the chosen approach in a realistic context.

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Architecture and design of a room-temperature feedback loop between cryogenic Qubits measurement and control chains

Département Systèmes et Circuits Intégrés Numériques

Laboratoire Systèmes-sur-puce et Technologies Avancées

01-09-2021

SL-DRT-21-0620

eric.guthmuller@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

A functional and useful Quantum Processing Unit (QPU) able to solve real problems on hundreds of Qubits will necessitate a way to correct errors introduced by quantum gates and Qubits decoherence. The foreseen way of doing this is to use error-correcting codes, such as surface codes for example. The common denominator to these error-correcting codes is the requirement to read regularly a subset of the Qubits and to apply operators to correct errors according to the measurement result. It is essential to reduce as much as possible the time between measurement and error correction, as in the meantime the Qubit error is still accumulating. The first objective of this PhD involves proposing an innovative low-latency (less than 1µs) digital architecture to correct errors in a real spin Qubits device. The second objective is to design this architecture on a FPGA board that is already used in Qubits measurement and control experiments. Finally, the student will do experiments on real Qubits devices placed in a cryostat to which the student will have access.

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Quantum computing for logistics and industrial applications

Département Ingénierie Logiciels et Systèmes (LIST)

Labo. ingénierie des langages exécutables et optimisation

01-03-2020

SL-DRT-21-0797

florian.noyrit@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Quantum computing sounds promising to solve computational problems that classical computing cannot address practically because of their complexity. However, despite its promises and the recent development of quantum technologies, industrial applications of quantum computing are so far limited. Nevertheless, recent developments of some quantum algorithms (e.g. Variational Quantum Eigensolver [1], Quantum Approximate Optimization Algorithm [2]), running on existing or upcoming quantum devices (NISQ - Noisy Intermediate-Scale Quantum) [3], suggest many opportunities for near/mid-term applications in solving some optimization problems. Logistics and industrial engineering are application fields that offer optimization problems (scheduling, planning, routing?) complex to solve with classical algorithmic. Some theoretical analysis and early experiments [4] already draft some viable applications for quantum computing techniques. However, because it is a living research topic, knowledge on these topics is scattered, unstable (new algorithms are proposed frequently), sometimes speculative, and not generalized yet. We therefore propose to explore the application of recent quantum computing techniques (notably hybrid algorithms and NISQ-applicable) on some optimization problems from our industrial projects. The objectives of this research work will be the followings: ? Select relevant optimization problems from our ongoing or past projects in fields of logistics and industrial engineering. ? Select quantum algorithms applicable to those problems from state of the art and state of the practice and implement them. ? Adopt or devise a benchmarking framework that can evolve along with the progresses in the field of quantum computing-based optimization. : computing time optimization, problems size, computer size ... ? Evaluation of the technical viability through concrete experiments. The evaluation will notably aim at analyzing the applicability factors such as the convergence properties of algorithms, the impact of the formulation of the problem on the effectiveness, the influence of the hardware architecture. More generally, the evaluation must give insights on the qualitative and quantitative thresholds (number of qubits [5], connectivity, noise?) that make the algorithm viable on NISQ devices (existing or upcoming). ? Propose and develop solutions to make the algorithms viable. For example, by adapting or extending the algorithms, proposing rewritings of the problem formulations, by implementing a particular compilation flows, by adapting the architecture of the execution platform... This work implies the access to actual or emulated quantum computing devices to run the experiments. Experiments are expected to be run on various platforms. This PhD will be carried out at Grenoble. [1] A variational eigenvalue solver on a photonic quantum processor, Peruzzo et Al., 2013 [2] A Quantum Approximate Optimization Algorithm, Edward Farhi and Jeffrey Goldstone and Sam Gutmann, 2014 [3] Quantum Computing in the NISQ era and beyond, John Preskill, 2018 [4] Quantum Computing Algorithms for optimised Planning & Scheduling (QCAPS), Dr Roberto Desimone et Al. 2019 [5] Guerreschi, G. G., & Matsuura, A. Y. (2019). QAOA for Max-Cut requires hundreds of qubits for quantum speed-up. Scientific reports, 9(1), 6903. The candidate should have good knowledege in one or more of the following topics : ? Quantum information and computation ? Combinatorial Optimisation ? Linear Algebra ? Algorithmic Complexity

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Integrated circuits to enhance the performance of resistive-based memories

Département Composants Silicium (LETI)

Laboratoire de Composants Mémoires

01-09-2021

SL-DRT-21-0859

gabriel.molas@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

The Phd objective is to explore fine and dynamic tuning circuit techniques, integrated nearby memory cells, to enhance the performance of RRAM.

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