Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Technological challenges >> New computing paradigms, circuits and technologies, incl. quantum
11 proposition(s).

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Contactless electronics under high-temperature and radiation exposures

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Gestion d'Energie Capteurs et Actionneurs

SL-DRT-20-0249

gael.pillonnet@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

The objective is to design a new generation of contactless electronics to be robust to high-temperature and radiation expositions. Based on the recently introduced ?contactless electronics? paradigm, the PhD student have to define new mechanical structures and electronics schemes to operate in harsh conditions and to offer analog- and digital-operations. This study is based on a complete breakthrough proposal compared to the classical transistor-based electronics to overcome the inherent physical limit of transistor at high-temperature. The PhD student will propose, model and simulate electro-mechanical micro fabricated structures to validate the theoretical principle recently announced by some senior-scientists in our laboratory. The project involves multi-disciplinary study including microelectronics, electromechanical MEMS devices, solid-state physics and gives an excellent opportunity for PhD student to cover a large scientific scope.

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Concrete Programming Model for computer with quantum accelerator

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Infrastructure et Ateliers Logiciels pour Puces

01-10-2020

SL-DRT-20-0364

Henri-Pierre.Charles@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Quantum computers will provide unprecedent performances thanks to a very different computing model from the classic computers. The information medium is no longer a 2 states bit but a qbit carrying analog information. Besides, the possibility of entangle a multitude of qbits and manipulate them in a coherent way will provide unprecedented computing power. These quantum computers, with specific applications, will be accelerators of for conventional computers and can not carry a full application. This type of heterogeneous architecture already exists: a GPU or a DSP are pro- grammed from a conventional processor. But in this case the calculation models are similar and the data use the same representation: the two's complement binary format to integer numbers, the IEEE 754 format for floating point numbers, UNICODE for characters, etc. In a quantum machine (as in the vision of DELFT University [3]), it will be necessary to mix two types of very different calculation models (Von Neumann and Quantum models) and data representation spaces that are also different. This thesis will explore different calculation models and ways to move from one model to the other. A programming language and tools for compilation to implement algorithms and make them operate on different platforms (hardware or simulated) will be the main outcome of the thesis. The candidate will have to learn and synthesize a certain number of knowledge: current quantum machines (via platforms of simulation and/or real machines), take into account the characteristics of the physical qbits performed at LETI, discover the calculation models adapted to quantum computation (ZX calculus [2]), assimilate the algorithms / applications [6] known in the quantum field. The subject is pluridisciplinary complex, but CEA is an ecosystem where all this knowledge is present both in the design of physical qbits, in the design of physical qbits, in the electronic, in terms of computer architecture and languages and UGA will provide knowledge, both at the algorithmic level and at the model level of programming level. Through the synthesis of knowledge, the candidate will propose new way to program quantum accelerators in connection with current programming languages [7] based on pre-existing models such as the calculated ZX [2]. With a classic part for the control and access to data and a quantum part for the accelerated part of the program. The classical applications [6] of the domain can be used as benchmarks and will demonstrate the value of the approach, other algorithms will be studied to identify possible candidate for quantum acceleration. [1] H. Bohuslavskyi, A. G. M. Jansen, S. Barraud, V. Barral, M. Cassé, L. Le Guevel, X. Jehl, L. Hutin, B. Bertrand, G. Billiot, G. Pillonnet, F. Arnaud, P. Galy, S. De Franceschi, M. Vinet, and M. Sanquer. Cryogenic subthreshold swing saturation in fd-soi mosfets described with band broadening. IEEE Electron Device Letters, 40(5):784787, May 2019. 3 [2] Niel de Beaudrap and Dominic Horsman. The ZX calculus is a language for surface code lattice surgery. arXiv preprint arXiv:1704.08670, 2017. [3] X. Fu, L. Riesebos, L. Lao, C. G. Almudever, F. Sebastiano, R. Versluis, E. Charbon, and K. Bertels. A Heterogeneous Quantum Computer Architecture. In Proceedings of the ACM International Conference on Computing Frontiers, CF '16, pages 323 330, New York, NY, USA, 2016. ACM. [4] Harald Homulle, Stefan Visser, Bishnu Patra, Giorgio Ferrari, Enrico Prati, Car- men G. Almudéver, Koen Bertels, Fabio Sebastiano, and Edoardo Charbon. Cry- oCMOS Hardware Technology a Classical Infrastructure for a Scalable Quantum Computer. In Proceedings of the ACM International Conference on Computing Frontiers, CF '16, pages 282287, New York, NY, USA, 2016. ACM. [5] Louis Hutin, Benoit Bertrand, Yann-Michel Niquet, Jean-Michel Hartmann, Marc Sanquer, Silvano De Franceschi, Tristan Meunier, and Maud Vinet. SOI MOS Technology for Spin Qubits. ECS Transactions, 93(1):3536, October 2019. [6] Ashley Montanaro. Quantum algorithms: an overview. November 2015. [7] Benoît Valiron, Neil J. Ross, Peter Selinger, D. Scott Alexander, and Jonathan M. Smith. Programming the quantum future. Communications of the ACM, 58(8):52 61, 2015. [8] Rodney Van Meter and Clare Horsman. A Blueprint for Building a Quantum Com- puter. Commun. ACM, 56(10):8493, October 2013.

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Integration of ULP neurons network based on Injection Locked Oscillators

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Gestion d'Energie Capteurs et Actionneurs

01-09-2020

SL-DRT-20-0418

franck.badets@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Neural Networks have demonstrated their superiority compared to Von Neumman computing machines for complex classification tasks. Embedding neural networks near the sensors (Edge IA) is a promising way to afford decision autonomy to sensor nodes. This could lead to a global decrease of the power consumption of sensor networks by decreasing the information rate between the nodes and the calculation center which will have also to provide a smaller amount of calculation. Decreasing the power consumption of neurones is a hot research topic as it is a key toward Edge IA. Beside digital implementations, some analog implementations are proposed, but these solutions are bulky and their power consumption is still high. The aim of the thesis work is to demonstrate the feasibility of the implementation of a neural network using Ultra Low Power Injection Locked Oscillators as neurones. Thesis work should lead to the silicon demonstration of learning ability of such networks. Applicant should have a good knowledge of statistical learning and neural networks in particular. He should have good knowledge of analog electronics. Theoretical study will necessitate strong expertise on both mathematics and modelling using python

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Multi-scale modeling of the electromagnetic quantum dot environment

Département Composants Silicium (LETI)

Laboratoire de Simulation et Modélisation

01-10-2020

SL-DRT-20-0637

helene.jacquinot@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Multi-scale modeling of the electromagnetic quantum dot environment In the near future, emerging quantum information technologies are expected to lead to breakthroughs in the world of high performance computing and secure communication. Among solid-state approaches, ?Silicon on Insulator? (SOI) based spin quantum bit (qubit) is an alternative approach to nowadays superconducting based one [1]. They are much more compact and have demonstrated over the last few years significant achievements, with long coherence time and fast single qubit rotation. A clear challenge is now to investigate the scalability issues going from single to multiple of the spin qubits in SOI, taking into account its associated classical CMOS platform used for control, read-out and initialization of the quantum state [2]. The main goal of this PhD work is to assess different strategies to implement spin control on 2D qubit arrays using microwaves signals. The candidate will i) characterize radio-frequency (RF) test structures at very low temperature using state-of-the-art equipment and compare results with dedicated electromagnetic simulations, ii) develop a toolbox to allow multi-scale optimization from single to qubit arrays, iii) integrate RF spin microwave control for 2D qubit array using CEA-LETI silicon technologies. This PhD work will be performed in the frame of a tripartite collaborative project between CEA-LETI, CEA-IRIG and CNRS-Institut Néel (ERC ?Qucube?). [1] Maurand, R. et al. A CMOS silicon spin qubit, Nat. Communications 7, 13575 (2016). [2] Meunier, T. et al. Towards scalable quantum computing based on silicon spin, Symp. on VLSI Technology, 2019.

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Cryogenic electronics to massively address silicon quantum bits

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Gestion d'Energie Capteurs et Actionneurs

SL-DRT-20-0675

xavier.jehl@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Research on quantum computing currently focuses on upscaling the number of qubits in order to reach useful calculation capabilities. The mature CMOS technology for circuits offers the opportunity to develop on-chip integration of CMOS spin-qubits together with classical electronics. Readout chips at sub-Kelvin temperatures form a key element in the massive addressing of a qubit matrix compared to nowadays solutions with cable-limited room-temperature instruments. Our previous studies on circuits made with the industrial 28-nm Fully Depleted Silicon on Insulator technology have demonstrated the operation of basic circuit elements down to temperatures as low as 20 mK with acceptable power dissipation. Using this toolbox of cryogenic circuits, the thesis concentrates on the design and operation of more complex cryogenic circuits in order to massively address CMOS-inspired qubits matrix at low temperatures. The ultimate goal is to readout 1000's of spin qubits in a line-column arrangement. The PhD student will explore alternative solutions for scalable readout such as the frequency multiplexing of electrometer sensors or of resonant oscillating circuits.

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Quantum computing for logistics and industrial applications

Département Ingénierie Logiciels et Systèmes (LIST)

Labo. ingénierie des langages exécutables et optimisation

01-03-2020

SL-DRT-20-0791

flroian.noyrit@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Quantum computing sounds promising to solve computational problems that classical computing cannot address practically because of their complexity. However, despite its promises and the recent development of quantum technologies, industrial applications of quantum computing are so far limited. Nevertheless, recent developments of some quantum algorithms (e.g. Variational Quantum Eigensolver [1], Quantum Approximate Optimization Algorithm [2]), running on existing or upcoming quantum devices (NISQ - Noisy Intermediate-Scale Quantum) [3], suggest many opportunities for near/mid-term applications in solving some optimization problems. Logistics and industrial engineering are application fields that offer optimization problems (scheduling, planning, routing?) complex to solve with classical algorithmic. Some theoretical analysis and early experiments [4] already draft some viable applications for quantum computing techniques. However, because it is a living research topic, knowledge on these topics is scattered, unstable (new algorithms are proposed frequently), sometimes speculative, and not generalized yet. We therefore propose to explore the application of recent quantum computing techniques (notably hybrid algorithms and NISQ-applicable) on some optimization problems from our industrial projects. The objectives of this research work will be the followings: ? Select relevant optimization problems from our ongoing or past projects in fields of logistics and industrial engineering. ? Select quantum algorithms applicable to those problems from state of the art and state of the practice and implement them. ? Adopt or devise a benchmarking framework that can evolve along with the progresses in the field of quantum computing-based optimization. : computing time optimization, problems size, computer size ... ? Evaluation of the technical viability through concrete experiments. The evaluation will notably aim at analyzing the applicability factors such as the convergence properties of algorithms, the impact of the formulation of the problem on the effectiveness, the influence of the hardware architecture. More generally, the evaluation must give insights on the qualitative and quantitative thresholds (number of qubits [5], connectivity, noise?) that make the algorithm viable on NISQ devices (existing or upcoming). ? Propose and develop solutions to make the algorithms viable. For example, by adapting or extending the algorithms, proposing rewritings of the problem formulations, by implementing a particular compilation flows, by adapting the architecture of the execution platform... This work implies the access to actual or emulated quantum computing devices to run the experiments. Experiments are expected to be run on various platforms. [1] A variational eigenvalue solver on a photonic quantum processor, Peruzzo et Al., 2013 [2] A Quantum Approximate Optimization Algorithm, Edward Farhi and Jeffrey Goldstone and Sam Gutmann, 2014 [3] Quantum Computing in the NISQ era and beyond, John Preskill, 2018 [4] Quantum Computing Algorithms for optimised Planning & Scheduling (QCAPS), Dr Roberto Desimone et Al. 2019 [5] Guerreschi, G. G., & Matsuura, A. Y. (2019). QAOA for Max-Cut requires hundreds of qubits for quantum speed-up. Scientific reports, 9(1), 6903. The candidate should have good knowledege in one or more of the following topics : ? Quantum information and computation ? Combinatorial Optimisation ? Linear Algebra ? Algorithmic Complexity

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Design of a 3D stacked smart imager dedicated to neural network processing

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Adéquation Algorithmes Architecture

01-10-2020

SL-DRT-20-0855

stephane.chevobbe@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

The 3D stacked silicon technologies allow the fabrication of new kinds of smart vision sensors by vertically coupling image sensor and specific processors or memories inside the same chip. Some research teams develop 3D stacked vision chip either to increase the quality of the sensor or to embed high powerful processors inside the chip closely coupled to the imager, as we did by developing the RETINE chip. Deep neural networks are widely used in many application domains including computer vision. A lot of research consists in increasing the power efficiency and decreasing the power consumption of embedded systems dedicated to neural networks execution. In this PhD thesis we propose to evaluate the opportunities offered by 3D stacked silicon technologies to question and envision new kind of digital 3D stacked vision chip embedding neural network hardware. In this PhD thesis we wish to study the contribution of 3D integration technologies in an intelligent imager integrating neural network processing functions. We will focus this study mainly on deep neural networks, however other types of neural networks can be evaluated. The architectural contribution expected from this thesis is the study and design of an efficient and low-power computing architecture that meets the high constraints imposed by deep neural networks, namely the need for very regular high-performance computing and the very high need for memory

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High speed wireline and optical communication at cryogenic temperature for quantum computing

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Silicium des Architectures Numériques

01-09-2020

SL-DRT-20-0892

yvain.thonnart@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

The promise for a universal fault-tolerant quantum computer robust to relaxation and phase errors of qubits faces a major scaling challenge, with thousands to millions of qubits to control and measure to implement the necessary quantum error correction codes. The information to exchange between the quantum devices at cryogenic temperature and the room temperature instrumentation equipments needs data throughputs above 1 Terabit/s to achieve in a reduced power budget to limit self-heating. This PhD topic aims to propose and realize energy-efficient high-speed communication architectures and circuits leveraging optical fiber transmission between the cryostat and the ambient temperature. The targetted innovation is to design and implement cryo-electronic CMOS circuits in FDSOI technology to realize communication functions such as SerDes, clock recovery and silicon-photonic modulator and receiver drivers tightly coupled to the quantum devices. These works will be integrated in a large development effort for a quantum computing Accelerator architecture based on electron spins in silicon, led by a pluridisciplinary team of physicists, technologists, CMOS designers and hardware and software architects.

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Automatic circuit instrumentation for the design of reliable systems

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-09-2020

SL-DRT-20-0901

chiara.sandionigi@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Fault tolerant circuits are currently required in several major application sectors and are going to be mandatory in future domains like autonomous vehicles. CAD tools are required to automate the insertion of fault tolerant mechanisms and validate the reliability properties of the circuit. Fault injection emerged as a widely accepted solution for the qualification plan of a design but with various challenges. In particular, the fault propagation analysis is not enough accurate or involves too much overhead in terms of computation time. The aim of the thesis is the implementation of a CAD tool for the automatic instrumentation of integrated circuits for an efficient fault propagation analysis after fault injection. The instrumentation modifies the circuit by inserting pieces of hardware to provide external controllability and observability of fault effects. Besides fault propagation analysis, the circuit instrumentation allows performing fault detection and error correction during system operation. The candidate must have experience in the design of embedded systems and knowledge of circuit reliability.

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Pixel wise coded aperture for new acquisition paradigms in CMOS Image Sensors based on active illumination

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Circuits Intégrés, Intelligents pour l'Image

01-10-2020

SL-DRT-20-0917

arnaud.verdant@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

Active illumination combined with image sensors bring the opportunity to extract a large amount of features about the observed scene that are generally not reachable to standard image acquisition approaches. This modality is now largely spread in industrial computer vision, consumer electronics and medical imaging applications. However, major challenges still need to be solved to increase the performances of such devices, and many associated research questions need to be addressed, with respect to the choices of the modulation and measurement strategy, the sensor architecture, or the signal processing techniques to employ for data analysis. The goal of this thesis is to jointly address those issues by first proposing a simulation framework aiming at finding the best trade-offs between light modulation and signal reconstruction approaches. Then, developing the system that will best fit to the derived specifications according to typical scene characteristics (ballistic or diffuse light behavior, depth range and resolution, ambient light levels, light source interferences?) will be addressed. This thesis will be structured in two main parts. The first part will tend to define an exploration framework based on a combination of physical modeling, physical measurements and deep learning approaches. Based on this tool, the second part will be dedicated to the development of an image sensor architecture using the issued specifications. The PhD student will benefit during his 3-years thesis of the expertise and the scientific excellence of the CEA Leti to attend objectives with a high level of innovation through international patents and publications. The dynamic and autonomous candidate will have a master or Engineer degree, specialized in electrical engineering and signal processing. A good knowledge of circuit design CAD and programming tools will be important (Cadence, Matlab, Python) and some basics in optics will be appreciated.

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Circuit partitioning for multi-FPGA platforms

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Calcul Embarqué

01-09-2020

SL-DRT-20-0941

francois.galea@cea.fr

New computing paradigms, circuits and technologies, incl. quantum (.pdf)

FPGAs are currently widely used for integrated circuit prototyping, or developing of hardware computing accelerators such as hardware implementations of deep neural networks. The circuits coming from these thematics can become very large in size and require to be implemented on a platform consisting in multiple tightly-coupled FPGAs. The Design Environment & Architecture Laboratory of CEA LIST is devoloping, as part of its Prototem software platform for circuit prototyping, a tool for partitioning an electronic circuit described as a hypergraph for execution on a given multi-FPGA platform. It consists in a multi-resource hypergraph partitioner, equivalent to state-of-the-art tools like hMetis or PaToH. The goal of this thesis is to adapt the academic problem of hypergraph partitioning to the objectives described by the circuit designers. More adapted modelings will have to be studied in terms of established performance criteria, including the cost function. New types of constraints from the profession will have to be integrated. Finally, a static mapping type modeling, taking into account constraints linked to the target platform integrating routing and signal multiplexing issues, will be proposed.

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