Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Technological challenges >> Emerging materials and processes for nanotechnologies and microelectronics
19 proposition(s).

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Study and Integration of Monolithic GaN Cascode Transistor

Département Composants Silicium (LETI)

Laboratoire Composants Electroniques pour l'Energie

01-10-2021

SL-DRT-21-0326

julien.buckley@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

LETI is currently transferring an AlGaN/GaN power electronics technology on 200mm silicon wafers to a renowned industrial partner in the field of power electronics devices (silicon, SiC). Gallium nitride-based (GaN) power electronics transistors can have either a normally-off (e-mode) or normally-on (d-mode) operation mechanism. For security reasons, there is a preference for e-mode devices. There are three main types of methods to obtain such functionality: either by using a p-type GaN gate, a conduction channel that includes a MOS stack (metal, oxide, semiconductor) or a cascode architecture (by assembling an e-mode and a d-mode device). The cascode architecture for GaN-based devices is today highly successful as it can be driven with similar strategies than the ones used for more traditional silicon parts and because of its good reliability. The work of this PhD will consist in conducting a study aiming to optimize the design of the device and identify its key technological steps (epitaxy, deposition, lithography, implantation...) necessary to its fabrication, followed by the coordination of the tasks necessary to its processing in LETI clean rooms. An analysis and interpretation of the obtained electrical measurements will be performed by using finished element simulations (TCAD using Synopsys environment).

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Lithography process for 3D high-resolution patterning

Département des Plateformes Technologiques (LETI)

Laboratoire

01-09-2021

SL-DRT-21-0409

jerome.reche@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Since 1960 the CEA-LETI (laboratory of electronics and information technology) is ones of main contributor of French innovation is electronics and new technologies. Its different entities are a real bridge between research and industry. One of them, the DPFT (technological platform department), includes the resources of manufacturing, the control and the associated environment, which allows to set up and to mature new processesto develop the future of electronics. Use of 3D structures to replace planar structures is one way to achieve this plan. Nevertheless, the current 3D structures, which are made and replicated, as microlens used in photonic field, use process scale for micrometer size and the new needs target sub-micronics size. The replication technology as high-resolution nanoimprint could adress this scaling challenge with yield improvement (time and cost reduction). The nanoimprint technology allows replication of 3D structure in one process step inside a functional material, this mean that the material imprint is the final use for application and not an intermediate one. The final aim of the thesis is the realization of 3D structures on a sub-micrometric scale (100 nm to 1 µm) and their replication. This involves firstly the creation of such structures using known but slow technology such as electron beam lithography associated with the transfer techniques in hard materials. Moreover, it will be necessary to characterize these structures at each stage in order to know their precise shape. In a second step, the candidate will be able to try to replicate these patterns with the laboratory nanoimprinting equipment and the various materials and processes already developed in the lab. The replicated structures will be finely characterize to evaluate morphological modification, defectivity obtained or possible non-uniformity. From these results, the candidate will have to implement a detailed analysis potentially associated with design of experiment (DOE) and the use of modeling to adapt the process and the starting structures to obtain the expected replication. The thesis contract will take place over 3 years with a gross monthly salary of 2 043.54? during the 1st and 2nd years, and 2 104.62? for the 3rd year. At the end, the skills developed by the PhD student enable him to work in many high technology sectors such as nano and microelectronics, materials chemistry or more generally data processing field.

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Interconnection of ultra-thin electronic components in stretchable flex for medical application

Département Composants Silicium (LETI)

Laboratoire Packaging et 3D

01-10-2021

SL-DRT-21-0466

jcsouriau@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Developments in flexible systems integrating ultra-thin silicon components and sensors offer new perspectives of application to the medical world. Indeed, it is conceivable to functionalize wearable patches, which allow the monitoring of vital and/ or physiological parameters such as heart rate, blood pressure, oxygenation of blood, body temperature etc... An important issue is the robustness of these systems under mechanical constraint. Depending on the location on the human body, the patch will have to endure more or less important stretches. The electrical interconnections in the flex with the silicon components, which are not stretchable will then be strongly stressed. The CEA-LETI has recently developed a generic wafer manufacturing process for flexible labels including thinned silicon components below 50 µm. However, the chosen flexible material was not stretchable. Within the framework of this thesis, new stretchable materials, robust and compatible with a wafer level integration will have to be identified. One of the objectives will also be the development of stretchable interconnection based on a biocompatible elastomer. This interconnection must be locally conductive and sufficiently adherent to support the patch manufacturing process and the maintenance of the chips throughout its use. The PhD student will take into account the developments of the CEA-Liten on an interconnection inspired by the structure of the legs of the gecko. Finally, with a view to reusing the added high-value components and improving the recyclability of the patch, this interconnection must also be repositionable and reusable.

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Development of advanced etch processes for new CMOS gate patterning

Département des Plateformes Technologiques (LETI)

Laboratoire Gravure

01-10-2021

SL-DRT-21-0472

aurelien.sarrazin@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

With quantum technology emergence, device architectures such as active and gate transistor are deeply modified. These nested structures impose a very high etch control to meet new device requirements. New challenges should be overcome to keep sub-20 nm pattern dimensions and also to increase material etch selectivity . To do so, we propose to develop Atomic Layer Etching (ALE) approaches. Thanks to these techniques, we should be able to multiply etch selectivity and to promote pattern shape fidelity by passivation and etch behavior dissociation. Characterization and mechanism understanding will help study evolution. Thus, we could be supported by numerous ways of characterization proposed by LETI's plaforms and a last generation plasma reactor. These studies take part of quantum development proposed by LETI structures for the next decade. Challenges, human and material support allow to propose comfortable conditions to lead these PhD program and to investigate result valorisation.

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Polarization sensitive pixels

Département d'Optronique (LETI)

Laboratoire d'Imagerie sur Silicium

01-10-2021

SL-DRT-21-0588

quentin.abadie@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

For certain mass productions markets (automotive, industrial control, depth mapping etc?), polarization pixels could be useful. PhD will address this domain and weight pros and cons of current solutions. Differentiating from current competitors polarization sensors with Metal grids, the thesis project aims to explore new design/process to improve performances.

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Accounting for the Environmental Impact of Digital Systems during the Design Phase

Département Systèmes et Circuits Intégrés Numériques

Laboratoire Systèmes-sur-puce et Technologies Avancées

01-09-2021

SL-DRT-21-0630

adrian.evans@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Currently, the green house gas emissions from digital systems are comparable to those from the aviation seector and unfortunately, they are following an exponential growth curve. This PhD thesis targets to realize a thorough analysis of the environmet impact due to the design phase et usage of large digital circuits. Following this analysis, the objective it to offer new tools and associated design methodologies to circuit designers, allowing to estimate et then reduce the environment impacts. During the design phase, it is targetted to reduce the amount of computing ressources, but the major gain will come from increasing the Energy efficiency and reduce the power enveloppe of digital system during its lifetime. This requires to analyse globally the system, from circuit level up to task delegation in the cloud. As a world leader in intelligent digital systems, the digital design departement targets to develop, through this PhD, a sober design flow that will be transfered to the industry. The PhD work will be using the overall design platform of the digital circuit and system departement, using different high performance computing systems as potential test-cases, and will define and optimize some cross layer optimization techniques.

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Numerical twins of strained interfaces involving MoS2, III-N and SiC obtained by combining experiments and simulations

Département des Plateformes Technologiques (LETI)

Laboratoire

01-10-2021

SL-DRT-21-0699

cyril.guedj@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

This transversal thesis aims at developing realistic and predictive atomic scale simulations to analyze the interfaces between a substrate and the deposited thin film in relationship with the STM and STEM measurements. This numerical tools will be useful to describe the behavior of atoms at the interfaces to understand and optimize the growth processes. To achieve this goal, an approach mixing the speed of machine learning force fields and the precision of ab-initio DFT calculations will be performed. It is necessary to use several level of descriptions adapted to the physical scale: ab-initio methods for electronic effects at the interface and empirical potentials to describe long-scale elasticity. The coupling between scales will enable a faster or deeper atomistic modeling of realistic systems. Two types of growth will be explored to develop this general methodology: a direct growth on MoS2 or a remote epitaxy on SiC. The use of a recently patended methodology will permit the extraction of the atomic positions from experimental data with the best available precision, which constitutes a major advantage in the verification and validation of all simulations by direct comparison with experiment. Ultimately, this thesis will provide numerical twins of materials and interfaces which should be predictive enough to enable realistic in-silico experiments. Hence, these numerical tools will be very useful to rapidly optimize the technology with maximum precision and confidence.

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Département des Plateformes Technologiques (LETI)

Laboratoire Gravure

01-10-2021

SL-DRT-21-0702

aurelien.tavernier@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

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Methods and digital twins for the implementation of eco conception in R&D from prototypes to pilot lines

Département des Plateformes Technologiques (LETI)

Labo Support et Interface Techno

01-10-2021

SL-DRT-21-0721

olivier.girard@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The analysis of environmental impact in an industrial context consists in the anticipation of the environmental impact for each phase in the life cycle of a product. This is often not taken into account when new technologies or processes are developed, even though the choices made can have a significant impact later on. You will work towards making the processes involved in making nanodevices the most eco-efficient as possible. This will start at the prototype stage by defining all the potential impacts, including those due to production up-scaling. For this you will need to consider 1) how to measure the environmental impacts 2) how to collect the data on energy and material use in pilot lines, 3) develop an understanding of impact transfer, 4) create tools to adapt the analysis of a pilot line to full scale industrial production. You will have access to data from the CEA pilot lines that will be used to develop digital twins for the pilot lines to test the effects of modifications on the eco-efficiency. You will also work closely with a team of multidisciplinary experts at CEA.

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Modelization and characterization of nano-compliant effects for localized epiaxial growth of GaN on Si substrates.

Département des Plateformes Technologiques (LETI)

Laboratoire des Matériaux pour la photonique

01-09-2021

SL-DRT-21-0730

guy.feuillet@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

In order to decrease the dislocation density induced by the different crystalline structures between the nitride semiconductor layers and the Si substrates they are grown onto, one often uses localised epitaxy methods. However, these result in the formation of other defects arising between the adjacent nucleation centers. We have developed an original localised epitaxy method by which the crystallites are deposited onto deformable nano-pilars, allowing these crystallites to join without creating any defect. The PhD work we propose aims at a better understanding, for a better control, of the mechanical and thermo-mechanical processes at pla during this process of nano-pendeo compliant epitaxy. This will be dealt with using finite element models so as to predict the mechanical behaviour of these complex nano-structured systems and by using an ensemble of structural nano-characterization tools for assessing the defect and strain distribution in the materials. From the reduction of defects in the epitaxial layers, we expect to address some of the main issues for a number of important applications related to these nitride materials in the opto- and micro-electronic domains.

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New approach for advanced logic devices contact plasma etching

Département des Plateformes Technologiques (LETI)

Laboratoire Gravure

01-10-2021

SL-DRT-21-0747

francois.boulard@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

CEA-Leti and partners are actively developing quantum computing based on silicon platform. While the interest of such technology is to be compatible with industry, some processes require improvements to achieve sub nanometer control. Among them contact etching is challenging. On billions of contacts etch simultaneously, the lateral critical dimension and the over etch of the stop layer should be mastered to reach dispersion below 1nm and less than 1nm consumption, respectively. To answer to these challenges, we propose to implement gas pulsing on fluorocarbon based plasma etch chemistry. Such approach cycles deposition of a reactive layer and its activation. While it allows theoretically to reach contact etching requirements, its practical demonstration should be done. The work will be mainly experimental and will take place on a 300mm clean room facility. First, experiments on silicon oxide and nitride blanket wafers will be carried out in order to understand the impact of gas pulsing on etch rates. The fluorocarbon reactive layer composition will be characterized by X-ray photoelectrons spectroscopy in order to improve the plasma surface understanding and to optimize the pulsing strategy. Second, learnings will be applied on contact patterned wafers. Cross section scanning electron microscopy and transmission microscopy will be use to evaluate the amount of aspect ratio dependent etching and stop layer consumption. These informations should confirm or reverse proposed mechanisms. Also, an exploratory study will target to quantify charged particles trapped at the contact bottom by capacitance voltage measurements. The final output of the work will be to implement contact plasma etch processes with gas pulsing on real qu-bits demonstrator wafers.

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Characterisation of microstructural effects related to the smartcut of SiC

Département Composants Silicium (LETI)

Laboratoire Intégration et Transfert de Film

01-11-2020

SL-DRT-21-0749

christelle.navone@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The automotive industry, with the recent expansion of the electric vehicles market, requires wide band gap devices, like SiC, that are more powerful and robust than the Si equivalent devices. However, SiC substrates are still very expensive and their supply is limited by the American and Asian monopoly of SiC wafer fabrication. The aim of this thesis is to create an innovative SiC substrate based on Smart Cut? technology : transfer of a thin SiC monocristalline layer on a cheaper substrate, typically SiC polycristalline wafer. The objectives of this research work are : - To deepen the understanding of SiC surface phenomena as function of the heat treatment of the wafers. This study will be based on annealing tests coupled with substrate surface analysis (AFM, PEEM, Raman, XPS) allowing the surface reconstruction mechanisms to be determined as function of the process parameters. The conditions of Graphene formation on the surface of the substrate should be particularly investigated in order to identify the solutions allowing to limit the SiC topological modification. - To understand the nature of SiC defects induced by the Smart-Cut technology step. The determination of the defects will be based on physico-chemical analysis such as photoluminescence, cathodoluminescence, etc. Chemical analyses based on KOH can also be used to reveal the defects on a larger scale. The propagation kinetics of these defects and their impact on the electrical conductivity will be investigated.

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DNA based 2D qbits network

Département des Plateformes Technologiques (LETI)

Laboratoire

01-10-2021

SL-DRT-21-0759

raluca.tiron@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

In nanotechnology in general and semiconductor industry in particular, there is an ever increasing need for smaller and more complex features at an ever lower cost. Some examples of applications are sub-10 nm features for creation of FinFETs, lateral (horizontal) and vertical gate-all around nanowires, single electron transistors and advanced non-volatile memories (STT-RAM, MRAM, OxRAM, etc.). To address the challenge of patterning at sub-10 nm features novel patterning approaches must be envisioned. DNA (deoxyribonucleic acid), by virtue of its inherent small diameter (2 nm), tendency to self-organize into various different morphologies and its possibilities for functionalization, offers the possibility to realize both two- and three dimensional structures at nanometer scale. The goal of this PhD work is to demonstrate the feasibility of nanostructuring the surface of a substrate using DNA origami as a mask, with an ultimate resolution of a few nanometer and with a density that is above the current state of the art in semiconductor industry. The focus of the thesis will lie on ever more complex features, while ensuring long-range order by conventional lithography guide patterns. The targeted demonstrator consists of manufacturing a 2D network of qbits based on DNA origami self-assembly.

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3D structuration by selective deposition

Département des Plateformes Technologiques (LETI)

Laboratoire

01-09-2021

SL-DRT-21-0760

guido.rademaker@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Traditionally, the industrial manufacturing of semiconductors consist of a loop of several process steps: deposition of materials - lithography - etching - stripping. This cycle is repeated multiple times to create a 3-dimensional structure. For applications of the type "More than Moore", a flexibility in the structuration is asked. For "More Moore" applications, the limits of the materials are found and innovative processes often consist of a combination of deposition - etching or lithography - deposition. This thesis is hosted at CEA-Leti's Advanced Lithography Laboratory, with access to traditionall photolithography, as well as self-organizing polymers such as block copolymers and DNA origamis. All of these materials have a capability to form 3D polymeric matrices. Instead of following the lithography by etching, we want to explore the hardening or functionalization by epitaxial growth, or a deposition step such as Chemical Vapour Deposition (CVD), Atomic Layer Deposition (ALD) or even Sequential Infiltration Synthesis (SIS). Depending on the application, a functionalization of the 3D surface by chemical treatment can be envisioned, to arrive at applications like biological sensors or meta-materials for optics and/or mechanics. The work in this thesis starts with a literature survey, followed by the evaluation of the feasability of integration at CEA-Leti. A 3D organic matrix will be created using the polymer and process chosen, followed by a step of growth or deposition, removal of the organic matrix, and 3D characterization and metrology of the structure, with as final result a morphological demonstrator. In case of promising results early in the thesis, in a collaboration with the applicative departments a functional demonstrator could be envisioned. The work finishes by the redaction of the thesis manuscript and its defence in front of a scientific jury.

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Use of polymers for the transfer of single-crystal thin films

Département des Plateformes Technologiques (LETI)

Laboratoire

01-04-2021

SL-DRT-21-0761

pierre.montmeat@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Organic polymers are versatile materials: they are good insulator, are easy to process for the elaboration of thin films and exhibit a high thermal resistance. For these reasons, they can be used for the elaboration of substrates for microelectronic purposes. In this field, the PhD work aims at the elaboration of innovative structures in which a single-cristal semi-conductor is attached to a polymer.

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Area selective deposition of oxydes for microelectronic

Département des Plateformes Technologiques (LETI)

Laboratoire

01-10-2021

SL-DRT-21-0781

chloe.guerin@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

In order to reduce the manufacturing costs of integrated circuits and continue their miniaturization, disruptive approaches based on the use of selective deposition processes are now being considered in addition to photolithography. Recent developments are mostly linked to the use of atomic layer deposition (ALD) which is a very suitable technique for the development of a selective process due to its high sensitivity to surface chemistry. ALD is a thin film deposition method based on the self-limited adsorption on a surface of gas phase precursors and surface reactions between precursor molecules and a reagent, allowing atomic-scale control of the thickness and quality of the deposited material. The objective of this thesis concerns the development of a localized selective deposition (ASD for Area Selective Deposition) based on the use of an organic layer allowing the deactivation of surface chemical reactions in ALD. This organic layer should act as an inhibition layer of ALD which allows selective deposition by zone. In the literature, this approach generally uses self-assembled monolayers (SAM) which may have limitations in terms of density and thermal or chemical stability. In this project, we will focus on the development of inhibition thin films deposited by vapor-based processes with the aim of finding a versatile method to allow the selective deposition of metal oxides. In addition to the selectivity with ALD deposits, the selection criteria will be the thermochemical stability of the inhibition layer in order to support the ALD process conditions as well as the possibility of depositing thick oxide layers. During this thesis, the PhD student will have access to several deposition techniques (ALD, PECVD, iCVD) as well as to a rich nano-characterization platform (ellipsometry, FTIR, contact angle, AFM, XPS, Tof-SIMS). These surface analyzes and thin film characterizations will allow to identify the best approach in order to obtain the highest possible selectivities. Fine characterization of organic and inorganic films at the nanoscale will also be carried out on patterned structures. One objective of this work will be also to highlight the mechanisms at the origin of selectivity as well as defect formation. Finally, the ASD process will be implement for the realization of an (opto) electronic demonstrator.

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Integration of Teraherts III-V transistors on silicon substrate for submillimeter wave applications

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-10-2021

SL-DRT-21-0796

herve.boutry@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Wireless technologies have advanced by leaps and bounds over the last several decades. Speeds have increased dramatically, connectivity has improved, and wireless network protocols, including Wi-fi and cellular, have become ubiquitous. Yet, despite a reasonnably fast, persitent wireless connection available in most parts of the world, today's wireless networks are still relatively limited in terms of how they can handle large volumes of data. The need for bandwith is growing and Terahertz communications, at frequencies of 300Ghz, could adress this problem. Multichip modules may present a possible solution to the mmW integration problem but at these frequencies, the lateral arrangement of chips on a carrier substrate comes at the cost of transmission line and contact losses. A preferred arrangement is the vertical 3D integration of mmW semiconductor devices or building blocs on top of the CMOS chip which could leverage the electrical specifications of the combined circuits.

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novel integrated circuit topologies using innovative capacitive components on silicon

Département Composants Silicium (LETI)

Laboratoire Stockage et Microsources d Energie

01-10-2021

SL-DRT-21-0814

sami.oukassi@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The objective of this thesis is to assess the potentiel of hybrid silicon capacitors developed at LETI as components in novel architectures of integrated energy conversion circuits. The hybrid capacitors exhibit a combination of unique properties in terms of energy density (ionic storage of the order of 40 mJ / mm3) and frequency response (dielectric storage demonstrated up to 30 GHZ), in addition to a technological realization on 200 mm silicon wafers. Within the framework of this project, it is proposed to design energy conversion circuits (eg. DC-DC converters)exploiting the intrinsic properties of the hybrid capacitors developed at LETI.

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HIGH PERFORMANCES ELECTROLYTES BY ALD FOR IONIC COMPONENTS

Département des Plateformes Technologiques (LETI)

Laboratoire

01-09-2021

SL-DRT-21-0857

messaoud.bedjaoui@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

This work aims to explore the feasibility of new ionic layers extremely thin obtained by ALD technique (Atomic Layer Deposition). These inorganic solid state layers are major candidates as high performance dielectric for main applications like high density capacitances or synaptic transistors for neuromorphic computing. The preliminary effort will be focused on the intrinsic characterization of ALD-based layers (thickness<20nm) using 2D short loops in order to identify attractive ones in terms of ionic conductivity and electric conductivity in comparison to solid electrolyte reference LiPON obtained by standard deposition technique. One of the challenges consists to adapt these ALD-based layers with 3D structures (high aspect ratio >200). The other challenge aims to reduce the ALD-based ionic layer thickness less than 5nm while still maintaining the advanced electric properties. This work covers multiple aspects including the ALD process, the ALD precursors, intrinsic layer development and technological integration on 3D components. Particular focus will be devoted to the physical-chemical, morphological and electrochemical characterizations of these layers.

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