Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PhD : selection by topics

Technological challenges >> Emerging materials and processes for nanotechnologies and microelectronics
23 proposition(s).

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Study and Integration of Monolithic GaN Cascode Transistor

Département Composants Silicium (LETI)

Laboratoire Composants Electroniques pour l'Energie

01-10-2021

SL-DRT-21-0326

julien.buckley@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

LETI is currently transferring an AlGaN/GaN power electronics technology on 200mm silicon wafers to a renowned industrial partner in the field of power electronics devices (silicon, SiC). Gallium nitride-based (GaN) power electronics transistors can have either a normally-off (e-mode) or normally-on (d-mode) operation mechanism. For security reasons, there is a preference for e-mode devices. There are three main types of methods to obtain such functionality: either by using a p-type GaN gate, a conduction channel that includes a MOS stack (metal, oxide, semiconductor) or a cascode architecture (by assembling an e-mode and a d-mode device). The cascode architecture for GaN-based devices is today highly successful as it can be driven with similar strategies than the ones used for more traditional silicon parts and because of its good reliability. The work of this PhD will consist in conducting a study aiming to optimize the design of the device and identify its key technological steps (epitaxy, deposition, lithography, implantation...) necessary to its fabrication, followed by the coordination of the tasks necessary to its processing in LETI clean rooms. An analysis and interpretation of the obtained electrical measurements will be performed by using finished element simulations (TCAD using Synopsys environment).

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Lithography process for 3D high-resolution patterning

Département des Plateformes Technologiques (LETI)

Laboratoire

01-09-2021

SL-DRT-21-0409

jerome.reche@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Since 1960 the CEA-LETI (laboratory of electronics and information technology) is ones of main contributor of French innovation is electronics and new technologies. Its different entities are a real bridge between research and industry. One of them, the DPFT (technological platform department), includes the resources of manufacturing, the control and the associated environment, which allows to set up and to mature new processesto develop the future of electronics. Use of 3D structures to replace planar structures is one way to achieve this plan. Nevertheless, the current 3D structures, which are made and replicated, as microlens used in photonic field, use process scale for micrometer size and the new needs target sub-micronics size. The replication technology as high-resolution nanoimprint could adress this scaling challenge with yield improvement (time and cost reduction). The nanoimprint technology allows replication of 3D structure in one process step inside a functional material, this mean that the material imprint is the final use for application and not an intermediate one. The final aim of the thesis is the realization of 3D structures on a sub-micrometric scale (100 nm to 1 µm) and their replication. This involves firstly the creation of such structures using known but slow technology such as electron beam lithography associated with the transfer techniques in hard materials. Moreover, it will be necessary to characterize these structures at each stage in order to know their precise shape. In a second step, the candidate will be able to try to replicate these patterns with the laboratory nanoimprinting equipment and the various materials and processes already developed in the lab. The replicated structures will be finely characterize to evaluate morphological modification, defectivity obtained or possible non-uniformity. From these results, the candidate will have to implement a detailed analysis potentially associated with design of experiment (DOE) and the use of modeling to adapt the process and the starting structures to obtain the expected replication. The thesis contract will take place over 3 years with a gross monthly salary of 2 043.54? during the 1st and 2nd years, and 2 104.62? for the 3rd year. At the end, the skills developed by the PhD student enable him to work in many high technology sectors such as nano and microelectronics, materials chemistry or more generally data processing field.

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Interconnection of ultra-thin electronic components in stretchable flex for medical application

Département des Technologies des NanoMatériaux (LITEN)

Laboratoire Composants Organiques

01-10-2021

SL-DRT-21-0466

julia.degirolamo1@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Developments in flexible systems integrating ultra-thin silicon components and sensors offer new perspectives of application to the medical world. Indeed, it is conceivable to functionalize wearable patches, which allow the monitoring of vital and/ or physiological parameters such as heart rate, blood pressure, oxygenation of blood, body temperature etc... An important issue is the robustness of these systems under mechanical constraint. Depending on the location on the human body, the patch will have to endure more or less important stretches. The electrical interconnections in the flex with the silicon components, which are not stretchable will then be strongly stressed. The CEA-LETI has recently developed a generic wafer manufacturing process for flexible labels including thinned silicon components below 50 µm. However, the chosen flexible material was not stretchable. Within the framework of this thesis, new stretchable materials, robust and compatible with a wafer level integration will have to be identified. One of the objectives will also be the development of stretchable interconnection based on a biocompatible elastomer. This interconnection must be locally conductive and sufficiently adherent to support the patch manufacturing process and the maintenance of the chips throughout its use. The PhD student will take into account the developments of the CEA-Liten on an interconnection inspired by the structure of the legs of the gecko. Finally, with a view to reusing the added high-value components and improving the recyclability of the patch, this interconnection must also be repositionable and reusable.

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Development of advanced etch processes for new CMOS gate patterning

Département des Plateformes Technologiques (LETI)

Laboratoire Gravure

01-10-2021

SL-DRT-21-0472

aurelien.sarrazin@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

With quantum technology emergence, device architectures such as active and gate transistor are deeply modified. These nested structures impose a very high etch control to meet new device requirements. New challenges should be overcome to keep sub-20 nm pattern dimensions and also to increase material etch selectivity . To do so, we propose to develop Atomic Layer Etching (ALE) approaches. Thanks to these techniques, we should be able to multiply etch selectivity and to promote pattern shape fidelity by passivation and etch behavior dissociation. Characterization and mechanism understanding will help study evolution. Thus, we could be supported by numerous ways of characterization proposed by LETI's plaforms and a last generation plasma reactor. These studies take part of quantum development proposed by LETI structures for the next decade. Challenges, human and material support allow to propose comfortable conditions to lead these PhD program and to investigate result valorisation.

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Distributed silicon photomultipliers electronic readout for particle localization and identification from a pixelated scintillator

Département Métrologie Instrumentation et Information (LIST)

Laboratoire Capteurs et Architectures Electroniques

01-10-2021

SL-DRT-21-0517

gwenole.corre@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The evolution of silicon photomultiplier technologies (SiPM) allows the implementation of pixelated measurements. The compactness of SiPMs opens up prospects for measurements distributed over larger and/or pixelated scintillator surfaces. The objective of the thesis is to provide a distributed electronic readout architecture in order to meet the application constraints of nuclear instrumentation. The work will start with a study of the state of the art of solutions to cope with the degradation of the signals from the detectors as well as the different methods for dealing with all application cases. This state of the art will define the constraints and the approach to integrate a distributed readout in the electronic board. In the second phase, the PhD student will realize a hardware architecture to manage a set of SiPMs to collect the light from pixelated scintillators. In order to assess the performance, various criteria will be studied such as spatial resolution, field homogeneity, detection efficiency and sensitivity, energy resolution, discrimination capacity. The developed system will be tested for one or more applications such as contamination mapping, radioactive source location and characterization, dosimetry mapping, particle beam characterization and calibration.

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Polarization sensitive pixels

Département d'Optronique (LETI)

Laboratoire d'Imagerie sur Silicium

01-10-2021

SL-DRT-21-0588

quentin.abadie@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

For certain mass productions markets (automotive, industrial control, depth mapping etc?), polarization pixels could be useful. PhD will address this domain and weight pros and cons of current solutions. Differentiating from current competitors polarization sensors with Metal grids, the thesis project aims to explore new design/process to improve performances.

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Numerical twins of strained interfaces involving MoS2, III-N and SiC obtained by combining experiments and simulations

Département des Plateformes Technologiques (LETI)

Laboratoire

01-10-2021

SL-DRT-21-0699

cyril.guedj@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

This transversal thesis aims at developing realistic and predictive atomic scale simulations to analyze the interfaces between a substrate and the deposited thin film in relationship with the STM and STEM measurements. This numerical tools will be useful to describe the behavior of atoms at the interfaces to understand and optimize the growth processes. To achieve this goal, an approach mixing the speed of machine learning force fields and the precision of ab-initio DFT calculations will be performed. It is necessary to use several level of descriptions adapted to the physical scale: ab-initio methods for electronic effects at the interface and empirical potentials to describe long-scale elasticity. The coupling between scales will enable a faster or deeper atomistic modeling of realistic systems. Two types of growth will be explored to develop this general methodology: a direct growth on MoS2 or a remote epitaxy on SiC. The use of a recently patended methodology will permit the extraction of the atomic positions from experimental data with the best available precision, which constitutes a major advantage in the verification and validation of all simulations by direct comparison with experiment. Ultimately, this thesis will provide numerical twins of materials and interfaces which should be predictive enough to enable realistic in-silico experiments. Hence, these numerical tools will be very useful to rapidly optimize the technology with maximum precision and confidence.

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Study of 3D pattern etch mechanisms for optoelectronic applications

Département des Plateformes Technologiques (LETI)

Laboratoire Gravure

01-10-2021

SL-DRT-21-0702

aurelien.tavernier@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Optoelectronic devices such as CMOS Image Sensors (CIS) require the realization of 3D structures, convex microlenses, in order to focus photons towards the photodiodes defining the pixels. These optical elements are mandatory for the device efficiency. Their shape and dimension are critical for device performances. These 3D structures are currently manufactured in Leti's cleanroom using successive steps of photolithography, photoresist reflow and plasma etching into the optically functional layer. Leti is at the state of the art on an alternative photolithography technics, so-called Grayscale. This process can produce a whole range of 3D structures not available with standard photolithography, such as concave, elliptic, pyramids and asymmetrical shapes. These structures could be used in a large number of application fields, like photonics and micro-displays (AR/VR). Just as CIS application, it is necessary to transfer these 3D patterns in an adapted functional layer using plasma etching. Currently the transfer by plasma etching of 3D patterns obtained with Grayscale photolithography is not well studied in literature. Consequently, this thematic is innovative and has a real benefit. The goal of this PhD thesis is to study and understand the etch mechanisms in order to control the shape and dimension of the transferred structures. The work will be very experimental and will be mainly performed in Leti's 300mm cleanroom. You will have access to a last generation plasma etch tool and numerous characterization technics. This thesis is in collaboration with the photolithography department and in interaction with different teams, such as the silicon platform and application department.

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Modelization and characterization of nano-compliant effects for localized epiaxial growth of GaN on Si substrates.

Département des Plateformes Technologiques (LETI)

Laboratoire des Matériaux pour la photonique

01-09-2021

SL-DRT-21-0730

guy.feuillet@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

In order to decrease the dislocation density induced by the different crystalline structures between the nitride semiconductor layers and the Si substrates they are grown onto, one often uses localised epitaxy methods. However, these result in the formation of other defects arising between the adjacent nucleation centers. We have developed an original localised epitaxy method by which the crystallites are deposited onto deformable nano-pilars, allowing these crystallites to join without creating any defect. The PhD work we propose aims at a better understanding, for a better control, of the mechanical and thermo-mechanical processes at pla during this process of nano-pendeo compliant epitaxy. This will be dealt with using finite element models so as to predict the mechanical behaviour of these complex nano-structured systems and by using an ensemble of structural nano-characterization tools for assessing the defect and strain distribution in the materials. From the reduction of defects in the epitaxial layers, we expect to address some of the main issues for a number of important applications related to these nitride materials in the opto- and micro-electronic domains.

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New approach for advanced logic devices contact plasma etching

Département des Plateformes Technologiques (LETI)

Laboratoire Gravure

01-10-2021

SL-DRT-21-0747

francois.boulard@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

CEA-Leti and partners are actively developing quantum computing based on silicon platform. While the interest of such technology is to be compatible with industry, some processes require improvements to achieve sub nanometer control. Among them contact etching is challenging. On billions of contacts etch simultaneously, the lateral critical dimension and the over etch of the stop layer should be mastered to reach dispersion below 1nm and less than 1nm consumption, respectively. To answer to these challenges, we propose to implement gas pulsing on fluorocarbon based plasma etch chemistry. Such approach cycles deposition of a reactive layer and its activation. While it allows theoretically to reach contact etching requirements, its practical demonstration should be done. The work will be mainly experimental and will take place on a 300mm clean room facility. First, experiments on silicon oxide and nitride blanket wafers will be carried out in order to understand the impact of gas pulsing on etch rates. The fluorocarbon reactive layer composition will be characterized by X-ray photoelectrons spectroscopy in order to improve the plasma surface understanding and to optimize the pulsing strategy. Second, learnings will be applied on contact patterned wafers. Cross section scanning electron microscopy and transmission microscopy will be use to evaluate the amount of aspect ratio dependent etching and stop layer consumption. These informations should confirm or reverse proposed mechanisms. Also, an exploratory study will target to quantify charged particles trapped at the contact bottom by capacitance voltage measurements. The final output of the work will be to implement contact plasma etch processes with gas pulsing on real qu-bits demonstrator wafers.

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Characterisation of microstructural effects related to the smartcut of SiC

Département Composants Silicium (LETI)

Laboratoire Intégration et Transfert de Film

01-11-2020

SL-DRT-21-0749

christelle.navone@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The automotive industry, with the recent expansion of the electric vehicles market, requires wide band gap devices, like SiC, that are more powerful and robust than the Si equivalent devices. However, SiC substrates are still very expensive and their supply is limited by the American and Asian monopoly of SiC wafer fabrication. The aim of this thesis is to create an innovative SiC substrate based on Smart Cut? technology : transfer of a thin SiC monocristalline layer on a cheaper substrate, typically SiC polycristalline wafer. The objectives of this research work are : - To deepen the understanding of SiC surface phenomena as function of the heat treatment of the wafers. This study will be based on annealing tests coupled with substrate surface analysis (AFM, PEEM, Raman, XPS) allowing the surface reconstruction mechanisms to be determined as function of the process parameters. The conditions of Graphene formation on the surface of the substrate should be particularly investigated in order to identify the solutions allowing to limit the SiC topological modification. - To understand the nature of SiC defects induced by the Smart-Cut technology step. The determination of the defects will be based on physico-chemical analysis such as photoluminescence, cathodoluminescence, etc. Chemical analyses based on KOH can also be used to reveal the defects on a larger scale. The propagation kinetics of these defects and their impact on the electrical conductivity will be investigated.

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DNA based 2D qbits network

Département des Plateformes Technologiques (LETI)

Laboratoire

01-10-2021

SL-DRT-21-0759

raluca.tiron@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

In nanotechnology in general and semiconductor industry in particular, there is an ever increasing need for smaller and more complex features at an ever lower cost. Some examples of applications are sub-10 nm features for creation of FinFETs, lateral (horizontal) and vertical gate-all around nanowires, single electron transistors and advanced non-volatile memories (STT-RAM, MRAM, OxRAM, etc.). To address the challenge of patterning at sub-10 nm features novel patterning approaches must be envisioned. DNA (deoxyribonucleic acid), by virtue of its inherent small diameter (2 nm), tendency to self-organize into various different morphologies and its possibilities for functionalization, offers the possibility to realize both two- and three dimensional structures at nanometer scale. The goal of this PhD work is to demonstrate the feasibility of nanostructuring the surface of a substrate using DNA origami as a mask, with an ultimate resolution of a few nanometer and with a density that is above the current state of the art in semiconductor industry. The focus of the thesis will lie on ever more complex features, while ensuring long-range order by conventional lithography guide patterns. The targeted demonstrator consists of manufacturing a 2D network of qbits based on DNA origami self-assembly.

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Use of polymers for the transfer of single-crystal thin films

Département des Plateformes Technologiques (LETI)

Laboratoire

01-04-2021

SL-DRT-21-0761

pierre.montmeat@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Organic polymers are versatile materials: they are good insulator, are easy to process for the elaboration of thin films and exhibit a high thermal resistance. For these reasons, they can be used for the elaboration of substrates for microelectronic purposes. In this field, the PhD work aims at the elaboration of innovative structures in which a single-cristal semi-conductor is attached to a polymer.

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Area selective deposition of oxydes for microelectronic

Département des Plateformes Technologiques (LETI)

Laboratoire

01-10-2021

SL-DRT-21-0781

chloe.guerin@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

In order to reduce the manufacturing costs of integrated circuits and continue their miniaturization, disruptive approaches based on the use of selective deposition processes are now being considered in addition to photolithography. Recent developments are mostly linked to the use of atomic layer deposition (ALD) which is a very suitable technique for the development of a selective process due to its high sensitivity to surface chemistry. ALD is a thin film deposition method based on the self-limited adsorption on a surface of gas phase precursors and surface reactions between precursor molecules and a reagent, allowing atomic-scale control of the thickness and quality of the deposited material. The objective of this thesis concerns the development of a localized selective deposition (ASD for Area Selective Deposition) based on the use of an organic layer allowing the deactivation of surface chemical reactions in ALD. This organic layer should act as an inhibition layer of ALD which allows selective deposition by zone. In the literature, this approach generally uses self-assembled monolayers (SAM) which may have limitations in terms of density and thermal or chemical stability. In this project, we will focus on the development of inhibition thin films deposited by vapor-based processes with the aim of finding a versatile method to allow the selective deposition of metal oxides. In addition to the selectivity with ALD deposits, the selection criteria will be the thermochemical stability of the inhibition layer in order to support the ALD process conditions as well as the possibility of depositing thick oxide layers. During this thesis, the PhD student will have access to several deposition techniques (ALD, PECVD, iCVD) as well as to a rich nano-characterization platform (ellipsometry, FTIR, contact angle, AFM, XPS, Tof-SIMS). These surface analyzes and thin film characterizations will allow to identify the best approach in order to obtain the highest possible selectivities. Fine characterization of organic and inorganic films at the nanoscale will also be carried out on patterned structures. One objective of this work will be also to highlight the mechanisms at the origin of selectivity as well as defect formation. Finally, the ASD process will be implement for the realization of an (opto) electronic demonstrator.

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Integration of Teraherts III-V transistors on silicon substrate for submillimeter wave applications

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-10-2021

SL-DRT-21-0796

herve.boutry@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Wireless technologies have advanced by leaps and bounds over the last several decades. Speeds have increased dramatically, connectivity has improved, and wireless network protocols, including Wi-fi and cellular, have become ubiquitous. Yet, despite a reasonnably fast, persitent wireless connection available in most parts of the world, today's wireless networks are still relatively limited in terms of how they can handle large volumes of data. The need for bandwith is growing and Terahertz communications, at frequencies of 300Ghz, could adress this problem. Multichip modules may present a possible solution to the mmW integration problem but at these frequencies, the lateral arrangement of chips on a carrier substrate comes at the cost of transmission line and contact losses. A preferred arrangement is the vertical 3D integration of mmW semiconductor devices or building blocs on top of the CMOS chip which could leverage the electrical specifications of the combined circuits.

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novel integrated circuit topologies using innovative capacitive components on silicon

Département Composants Silicium (LETI)

Laboratoire Stockage et Microsources d Energie

01-10-2021

SL-DRT-21-0814

sami.oukassi@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The objective of this thesis is to assess the potentiel of hybrid silicon capacitors developed at LETI as components in novel architectures of integrated energy conversion circuits. The hybrid capacitors exhibit a combination of unique properties in terms of energy density (ionic storage of the order of 40 mJ / mm3) and frequency response (dielectric storage demonstrated up to 30 GHZ), in addition to a technological realization on 200 mm silicon wafers. Within the framework of this project, it is proposed to design energy conversion circuits (eg. DC-DC converters)exploiting the intrinsic properties of the hybrid capacitors developed at LETI.

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HIGH PERFORMANCES ELECTROLYTES BY ALD FOR IONIC COMPONENTS

Département des Plateformes Technologiques (LETI)

Laboratoire

01-09-2021

SL-DRT-21-0857

messaoud.bedjaoui@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

This work aims to explore the feasibility of new ionic layers extremely thin obtained by ALD technique (Atomic Layer Deposition). These inorganic solid state layers are major candidates as high performance dielectric for main applications like high density capacitances or synaptic transistors for neuromorphic computing. The preliminary effort will be focused on the intrinsic characterization of ALD-based layers (thickness<20nm) using 2D short loops in order to identify attractive ones in terms of ionic conductivity and electric conductivity in comparison to solid electrolyte reference LiPON obtained by standard deposition technique. One of the challenges consists to adapt these ALD-based layers with 3D structures (high aspect ratio >200). The other challenge aims to reduce the ALD-based ionic layer thickness less than 5nm while still maintaining the advanced electric properties. This work covers multiple aspects including the ALD process, the ALD precursors, intrinsic layer development and technological integration on 3D components. Particular focus will be devoted to the physical-chemical, morphological and electrochemical characterizations of these layers.

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Integration of scalable arrays of quantum dots on silicon

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-09-2021

SL-DRT-21-0883

benoit.bertrand@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

Most of the silicon spin qubit demonstrations were made with linear arrays of quantum dots. However increasing the qubit interconnectivity seems necessary in order to implement efficient quantum error correction protocols. In terms of architecture, this implies transitioning to two-dimensional quantum dot arrays. Grenoble is among the leading groups on this topic with the first demonstrations of elementary 2D arrays on GaAs heterostructures at Neel Institute. The proposed study will aim at implementing such arrays on silicon technology and explore ways to transition

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Development of two-dimensional (2D) GaSe / InSe heterostructures for the realization of new concepts of nano- and opto-electronic devices that save on critical elements III

Département des Plateformes Technologiques (LETI)

Laboratoire des Matériaux pour la photonique

01-11-2021

SL-DRT-21-0973

berangere.hyot@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

With the very strong growth in the number of connected objects, which should almost triple, from 8.74 billion in 2020 to 25.4 billion in 2030, access to raw materials is becoming a major economic and geopolitical issue for the field of nanoelectronics. In order to develop sustainable nanoelectronics, it becomes necessary to design and produce devices (memories, optoelectronic components, etc.) by reducing or substituting their critical constituent elements. The notion of criticism can cover many aspects; a raw material can be classified as critical because of the available world reserves, production monopolies and possible associated geopolitical conflicts, the economic weight of the material on the balance of one or more countries or even ethical reasons (working conditions or environmental impact of extraction conditions). For example, many light emitting and light sensors devices (laser sources, light emitting diodes, photodetectors / imagers, etc.) are based on III-V semiconductors (alloys composed of elements from columns III and V of the periodic table). However, some of these elements, such as gallium (Ga) and indium (In), are now considered critical by the European Commission and it is urgent to reduce their consumption. Two-dimensional (2D) or lamellar III-VI (GaSe and InSe) semiconductors made up of only a few atomic monolayers now appear very promising for designing new architectures of optical sensors or memory cells that save on III elements. Compared to a conventional III-V component, a gain of 5 orders of magnitude can be expected on the consumption of Ga and In. Today, most devices based on III-VI materials presented in the literature are prepared by mechanical exfoliation of bulk crystals of GaSe or InSe, a technique allowing to carry out proofs of concept (the typical average dimension of exfoliated crystals is a few µm) but incompatible with the large scale and low cost manufacture of these components. The objective of the thesis is to work on the development of MOCVD growth of III-VI materials and their heterostructures directly on large-dimension silicon substrates (diameter = 300 mm). It should be noted that the combination of this growth technique with the use of silicon substrates makes the results of this work directly compatible with the production tools of microelectronics. The structural properties of these heterostructures will be investigated by X-ray diffraction (XRD), atomic force microscopy (AFM), transmission electron microscopy (TEM) and Raman spectroscopy. Their physical properties (electronic or optoelectronic) will be explored through the production of suitable devices. A previous study made it possible to overcome a certain number of difficulties linked to the integration of these materials and to implement various technological bricks (lithography, identification of compatible chemistries?) for the realization of functional devices. We will focus in this new thesis on the realization of two types of devices: optoelectronic devices (mainly photodetectors) and memory cells (or memristors). In both cases, we plan to work on vertical heterostructures where the properties of the silicon substrate will be taken advantage of. The expectations of these devices are wavelength selectivity adjustable from UV to IR and good conversion efficiency for photodetectors and a low operating voltage for memory cells allowing low-power electronics applications (neural networks for example). A theoretical approach involving ab initio calculations of GaSe / InSe superlattices with determination of the electronic and optical properties of different structures will support the experimental development described above and may serve as a guide in the design of new functional heterostructures (whether dedicated to photodetection or resistive memories). The candidate, depending on his/her sensitivity, can either get involved in the development of these mathematical models or participate in their analysis with the collaborators in charge of the study.

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Intra-die stress metrology: a new parameter for inline process control

Département des Plateformes Technologiques (LETI)

Laboratoire Propriétés des Matériaux et Structures

01-11-2021

SL-DRT-21-0974

lionel.vignoud@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

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Localised Gallium Nitride growth on silicon for the next generation of power electronic devices ? essential for electric vehicles and renewable energy

Département Composants Silicium (LETI)

Laboratoire Composants Electroniques pour l'Energie

SL-DRT-21-0996

julien.buckley@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

As renewable energy and electric vehicles become increasingly integrated into society, we require ever increasing efficiency. Gallium nitride is currently used in lateral components, but vertical structures are essential to move to the next level. With localised growth on silicon wafers, we can fabricate these devices at low cost without affecting their performance. The PhD will aim to perform localised growth on nano and micro patterns on 200 mm silicon wafers. The student will study the growth selectivity and the form of the growth islands by SEM, followed by dislocation (defect) density analysis by cathodoluminescence. In addition, the student will work with advanced scanning probe techniques, such as SCM (scanning capacitance microscopy) and SSRM (scanning spreading resistance microscopy) in order to evaluate the electrical characteristics of the structures, and assess their compatibility with power electronics devices. Finally, the student will fabricate some simple diode test structures to evaluate their electrical performance.

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Exploration and Integration of new devices in the 3DSL imager technology platform

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-10-2021

SL-DRT-21-1003

joris.lacord@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The 3DSL imager process technology is currently in development in Crolles300. It is based on a 3D sequential integration, with the pixel photosite integrated into a first layer of silicon, and the read out transistors built on top into a second thin layer of silicon. We are currently developing this technology to achieve very dense global shutter pixels (below 2um pitch); and as a next step we want to explore the potential of the 3DSL technology for very dense SPAD pixels. The objective of the thesis is to explore the challenges associated with the co-integration of new devices in the thin layer of silicon. For the SPAD quenching circuit, new devices are required including high voltage management transistors like EDMOS with constraints in terms of performance, reliability and dense design rules. The Ph.D work will cover many aspects with strong interactions with the design teams to understand the requirement to achieve SPAD layout down to 3um pitch, transistor architecture design and process integration, as well as elementary device characterization, simulation and modeling to understand the specific behavior of the transistors on thin film (floating body effect, etc?). The end goal is to contribute to the first functional demonstrator integrated on 300mm wafers. The student will be located in Crolles and/ or in Grenoble as the PhD work will be jointly driven by STMicroelectronics and CEA-LETI.

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Impact of InGaN quantum wells design and composition on the performance of micro-LEDs

Département d'Optronique (LETI)

Laboratoire des Composants Emissifs

01-11-2020

SL-DRT-21-1131

fabian.rol@cea.fr

Emerging materials and processes for nanotechnologies and microelectronics (.pdf)

The growth and fabrication of InGaN/GaN blue LEDs have reached a high degree of maturity thanks to their extensive use in the field of lighting. Thanks to their robustness and high efficiency, these LEDs are seen as promising candidates to make high-luminance and high resolution micro-displays for the field of augmented reality. However, the size of µLEDs composing the pixels of micro-displays are of a few micrometers. At these dimensions, the non-radiative recombination of electrons and holes occurring on the defect present at the sidewalls becomes dominant and degrade the performances. The passivation of these defects is the usual way to recover a higher efficiency. In addition, the lateral diffusion of carriers in InGaN quantum wells (QW) should also play a role on the performance of µLEDs by controlling the migration of electron and holes to the defective sidewalls. Over the last 10 years, researchers have gained a much better understanding of the physics of InGaN QW in large LEDs and they have optimized the epi-structures accordingly. However, going from macro to micro-LEDs have created new constraints (mainly the non-radiative recombination at the sidewalls). For this PhD, we propose to study the impact of InGaN QW design and composition on carrier diffusion properties and their impact on the performance of µLEDs. The student will be in charge of growing quantum wells and complete LEDs structures by MOCVD and will characterize them thoroughly. A large part of the PhD will be dedicated to the spectroscopic and electro-optical characterization of the samples that will be completed by structural characterization.

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