Scientific Direction

Sciences pour l'ingénieur >> Chimie physique et électrochimie
14 propositions.

Hardware support for interprocess communications in multi-core circuits

This study aims at improving the performances of synchronization primitives (barriers, distributed mutexes, etc.) in multicore integrated circuits, by offering architectural improvements for transport of synchronization messages, and hardware/software accelerators for the most performance-constrained primitives. Synchronization primitives indeed are a significant performance bottleneck in multicore systems. They are usually carried out through point-to-point exchanges of synchronization messages, controlled by the OS, which signal pending and occurred events (e.g. spinlock release or process waiting for a barrier). The delays introduced by these messages are all the longer as involved computing cores are numerous, which justifies the need of specific architectural features. The proposed research work aims at elaborating and implementing evolution of multicore architectures to accelerate transfers of synchronization messages (e.g. dedicated ?service interconnect?, multicast messages?). Besides, a study of real-life applications, representative of Cloud computing or HPC, will help identify the most performance-impacting synchronization primitives as candidates for joint hardware/software optimization. Works will take place in digital architectures lab of CEA-Leti, in collaboration with embedded software lab. These teams gather the relevant hardware (architectures, IP blocks) and software (OS, modeling) skills to fulfill this study. They also offer advanced prototypes of multicore chips and hardware emulation tools, enabling real-life experimentation of designed solutions. Required background: multicore architectures, VHDL & C programming languages, EDA tools, notions on OSs.

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire Intégration Silicium des Architectures Numériques Start Date : 01-09-2015 ECA Code : SL-DRT-15-0005 Contact : jerome.martin@cea.fr

Space, time and frequency diversity for accurate range and angle of arrival measurement in UWB

The objective of the PhD is to explore the use of a 2-4 antennas subsystem with an Ultra-Wide-Band (UWB) RF front-end to bring angle of arrival estimation. The research aims to analyze by models the impact of the propagation, the antennas and the RF path imperfections on the estimation, to establish performance bounds and to propose architectural solutions and algorithms. To achieve this goal, the principle is to rely on several estimation techniques, separately or jointly, using phase information, ultra-precise TOA estimations and frequency diversity. During the course of the PhD, real data will be exploited from existing UWB ICs and channel sounding campaigns data obtained thanks to measurement facilities and support at CEA-Leti. This research will bring a major innovation to go beyond the classical time of arrival estimation of existing integrated implementations used in precise real time location systems. The research will be applied to a use case in the medical area dedicated to visually impaired persons. Required background: Knowledge about communication systems, signal processing, RF architectures and some basics about antennas, propagation, RF circuits and measurements. Type of work : Bibliography (10%), Modelling (30%), Simulation (40%), Measurements (10%), Thesis and Papers Writting (10%)

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire Architectures Intégrées Radiofréquences Start Date : 01-10-2015 ECA Code : SL-DRT-15-0008 Contact : laurent.ouvry@cea.fr

Definition and implementation of a methodology for absolute measurement of radioactivity of a sample irradiated in a nuclear reactor

Dosimetry in reactor aims to determine the neutron fluence received during an irradiation and to characterize the spectrum (energy distribution of neutrons). This technique is based on the analysis of the radioactivity of irradiated dosimeters, composed of pure metals or alloys. The activity measurement of these samples is performed by gamma- or X-ray spectrometry of low-energy radiation (<100 keV). Radiations involved have many difficulties to be measured accurately, especially when the measurement must be made absolute. Characterization of a new dosimeter implies creating a standard specifically adapted and validated for the measurement conditions. The work will consist initially to establish the state of the art of the measurement techniques and to identify the isotopes of interest. This assessment will bring out the major limitations in the current methods and will allow searching new solutions to address both the theoretical and experimental approach. The study will induce theoretical analysis and modeling of radiation-matter interactions and an experimental part with the preparation and implementation of spectrometry measurements. The proposed methodology will be validated on known radioisotope before being tested on new radioisotopes. The work will be done at LNHB (CEA / Saclay) and at the MADERE platform at SPEx/LDCI (CEA / Cadarache).

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Département : DM2I (LIST) Laboratory : Laboratoire de Métrologie de l'Activité Start Date : 01-10-2015 ECA Code : SL-DRT-15-0021 Contact : laurent.ferreux@cea.fr

Program slicing applied to wireless sensor network protocols

The CEA LIST, based in Palaiseau (near Paris, France), is a key software systems and technology research center working on embedded systems (architecture and design of systems, methods and facilities for software and system dependability, and intelligent vision systems), interactive systems, signal detection and processing in partnership with the major industrial players in the nuclear, automotive, aeronautical, defense and medical fields. The Software Security Lab of the CEA LIST develops tools for verification and validation of software and software/hardware systems. One of these tools, Frama-C (http://frama-c.com), is a framework for analysis of C software. Today, it has an iplementation of program slicing, but does not offer a verified implementation that would make it possible to verify the simplified program instead of the original one. Appeared recently, wireless sensor networks are used in various domains (trasport, defense, building, automobile, etc.) and provide en efficient means to collect and transfer data without installing a network of wired devices, that would be much more costly if even possible. This Ph.D. aims at developing a formally verified technique of program slicing, implementing it in the context of the Frama-C framework and applying it to verification of protocols of wireless sensor networks. A first step of the work will consist in formalizing slicing techniques and in verifying them formally. The verification will rely on a formalization using an interactive proof assistant like Coq. Existing partial formalizations can be used as a starting point of this step. Next, this techniques will be implemented in the context of the Frama-C framework. The implementation can use existing analyzers (e.g. dependence analysis) or implement new ones. Finally, the new tool will be used to facilitate verification of protocols of wireless sensor networks. The study will include selected representative properties and will apply the methodology of verification relying on slicing and verification of the simplified program instead to original one. The candidate will have Master's degree, or equivalent, in Computer Science, preferably in Software Verification and Validation, and good knowledge of formal methods.

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Département : Département Ingénierie Logiciels et Systèmes (LIST) Laboratory : Laboratoire pour la Sûreté du Logiciel Start Date : 01-01-2015 ECA Code : SL-DRT-15-0043 Contact : Nikolay.Kosmatov@cea.fr

Very High Temperature DC/DC embedded power supply

The availability of Wide BandGap active components (GaN, SiC) has enabled placing power electronics converters (actuator control, variable speed drives ...) in high ambient temperatures > 200 ° C . However, many hard spots remain, particularly the constraints imposed by passive components. A promising way of exploration is to increase the switching frequency to reduce passives components and then to allow technological leaps. For this, a hybrid approach, an integrated part with a discrete part will be studied in order to achieve an essential function: DC / DC converter with insulation at high temperatures. The work will focus in part on the study of a SoI integrated circuit for controlling the high frequency DC / DC converter and secondly on integrating passives, especially the transformer. The thesis will be conducted in co-management between the CEA and the Laboratoire Ampere. The expected results are a feasibility study, conducting a demonstration and evaluation in a high temperature environment for aerospace applications and down hole drilling. The focus will be on the scientific content with an exigency on paper publications and on industrial innovation (patent). Funding will be provided for the construction of a demonstration to support the theoretical aspects of the work.

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Start Date : 01-10-2015 ECA Code : SL-DRT-15-0077 Contact : dominique.bergogne@cea.fr

Monitoring of high temperature effects on CMOS circuits

Deep sub-micron technologies become unavoidable even for critical applications in fields like automotive or nuclear industry. This evolution may have an important impact on the reliability of electronic systems involved in such applications in the absence of pro-active mitigation approaches. This thesis will be mainly focused on the influence of thermal aspects, e.g. high-temperature and thermal cycles, on the reliability of CMOS circuits. Monitoring solutions should be defined for electronic systems implemented on PCB and/or FPGA. These solutions and should enable on-line monitoring and have limited interference with the mission circuitry. Required background: - Microelectronics - Spice - VHDL and/or Verilog - FPGA prototyping

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire De Fiabilisation des Systèmes Embarqués Start Date : 01-09-2015 ECA Code : SL-DRT-15-0083 Contact : valentin.gherman@cea.fr

Event-based, bio-inspired coding and unsupervised learning for Deep Neural Networks, using artificial synapses

The last couple of years have seen a renewed interest in deep learning and deep neural networks (DNNs). Advances in hardware and in particular the use of high-end graphic processing units (GPUs) have enabled the realization of large and powerful networks [1], that are the first pattern recognizers capable of human-competitive performances on handwritten characters recognition, traffic signs recognition or face recognition [2]. More generally, DNNs today outperform all other machine learning techniques in the fields of image classification, scene labeling and speech recognition. They are already used by companies like Google or Facebook to classify the huge amount of data published on their social networks. Because DNNs are very similar to the organization of the visual cortex in the brain, there is today a convergence between computational neuroscience and DNNs and deep learning, which are seen as a step towards realizing strong AI [3]. DNNs are therefore a Key Enabling Technology for realizing intelligent, autonomous systems, like domestic and service robots and more generally, Internet of smart Things (IoT) that need to be able to sense and identify their visual and/or auditory environment. Nowadays, the DNNs used in information processing are implemented in software, using digital coding of the data (every pixel of an image is coded with a decimal number for example). The data processing is done image by image and is therefore entirely synchronous and sequential. This is different from the biological visual system, where the visual data stream is asynchronous and continuous and is made of spikes transmitted by the optical nerve. Moreover, the learning in DNNs is generally done using back-propagation, which is a classical mathematical optimization algorithm, very different from the biological learning algorithms in the brain. The objective of this thesis is to increase the convergence between the formal models of DNNs and the visual cortex models coming from the neurosciences. We propose to study the use of neuro-inspired event-based (or spike-based) coding [4][5] for DNNs, along with the use of neuro-inspired unsupervised learning methods, such as Spike-Timing-Dependent Plasticity (STDP) [6][7]. This thesis proposes an original approach and is firmly interdisciplinary. The Ph.D. student will be based in an electronics and signal processing lab, with an advisor from the field, and will be supervised by a neuroscientist specialized in the visual system in the brain.

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire De Fiabilisation des Systèmes Embarqués Start Date : 01-09-2015 ECA Code : SL-DRT-15-0102 Contact : olivier.bichler@cea.fr

Hardware acceleration for homomorphic encryption

The emergence of cloud computing and cyber-physical systems has led to consider security in data treatment as a major concern. In order to insure the confidentiality of managed data, encryption is today widely used. In 2009, C. Gentry [1] proposed the first fully homomorphic encryption system, enabling to compute preliminary encrypted data without decrypting them. This progress has opened a significant number of new industrial and research perspectives. However, in spite of many recent progresses [2,3], a significant number of limitations remain, especially regarding performance of these systems and their important memory requirements. This thesis aims at exploring the development of dedicated hardware accelerators for homomorphic encryption, facing up to these issues. To this end, the first step will be to explore existing algorithmic approaches in order to highlight their hottest parts and evaluating their acceleration opportunities. In a second step, an innovating hardware architecture to optimize the homomorphic encryption treatment will be proposed. This architecture should significantly accelerate the current state-of-the-art performance to open new application perspectives. [1] C. Gentry, "A Fully Homomorphic Encryption Scheme", Ph.D. dissertation, Stanford University, 2009. [2] C. Moore et al., "Practical Homomorphic Encryption: A Survey", ISCAS, 2014. [3] C. Aguilar-Melchor et al., "Recent advances in homomorphic encryption", IEEE Signal Processing Magazine, 2013.

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire Calcul Embarqué Start Date : 01-10-2015 ECA Code : SL-DRT-15-0179 Contact : alexandre.carbon@cea.fr

Emerging Non-volatile Memories Impact on Operating Systems

Abstract Emerging non-volatile memories will allow to replace DRAM used as computer main memories as well as, partially, Flash and hard-disk drives used as mass memory. These memory components will be denser, cheaper and consume less than DRAM. This thesis aims at revisiting operating systems organization to take benefit of their non-volatility to optimize computers performances and power consumption. Context Operating systems(OS) are designed to work with a DRAM main memory and a Flash or hard-disk-drive mass memory. The emergence of these new non-volatile components will allow to revisit this memory hierarchy and require a reorganization of operating systems to take benefit of it. Important gains in energy and performance are expected. Goals - Study of these new memory components impact on some OS sub-systems as virtual memory, file system, or boot, and, especially, of power consumption reduction opportunities, - Prototyping and performance analysis of modifications of the operating system exploiting these memories functionalities, - Recommendations on such future computers memory architecture, based on the results of this study. Environment This thesis will take place at CEA-LETI Grenoble, in the laboratory specialized on software linked to new hardware architectures, in cooperation with the group working on emerging memory design. Education Computer science diploma got from a university or an engineering school. Good knowledge of operating systems, and C language programing. Type of work - Bibliography: emerging memories, operating system architecture (~20%), - Proposals for operating system modifications (~30%), - Implementation and experimentation of some of these proposals (~40%), - Conclusions and report writing (~10%).

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire Infrastructure et Ateliers Logiciels pour Puces Start Date : 01-09-2015 ECA Code : SL-DRT-15-0199 Contact : michel.harrand@cea.fr

Development of high temperature solar selective absorber with high air stability

In the panel of renewable source of energy, concentrated solar power (CSP) technology seems to be very promising way for produce electricity from the sun. This technology use the direct irradiation from the sun, this light is concentrated by a field of mirror on a receiver to heat a fluid. This thermal power is converted on to electricity by a thermodynamic cycle. One of the huge advantages of this technology is the possibility to use a thermal storage to produce the electricity during the night also. The receiver is composed with tubes with an absorber coating on the surface to absorb the solar radiation and transfer the heat on the fluid circulating inside the tube. This coating must have a high solar absorbance (>90%) and a low emitance (<10%) at the working temperature. In term of durability, this coating must be stable during more than 25 year without decreasing there performances. To increase the efficiency of the CSP plant the working temperature must be increasing from around 400 °C to 600 °C. The subject of this thesis is to work on the development of selective solar absorber coating with a high performance up to 600°C with high stability in the air (25 year of life time). This work is proposed in collaboration with the Laboratory of Thermal System (CEA) at the National Institute of Solar Technology (near Chambery, France) and the Department of Thin Films (C2SP) of the Institute Jean Lamour (Nancy, France). During the thesis, the first step will be the choice of materials; the second step will be the optical simulation of the coating properties to find the best design of layers and the appropriate materials. In the third phase, experimental deposition of coating will be tested by using Physical Vapor Deposition technics. For this part of work, high power impulse magnetron sputtering (HPIMS) technics for coating will be evaluated. Optical characterization and the durability of coating will be tested to validate the performance of these new materials. In fine, a demonstration on a real tube will be realized with an industrial partner for the proof of concept.

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Département : Département Thermique Biomasse et Hydrogène (LITEN) Laboratory : Start Date : 01-10-2015 ECA Code : SL-DRT-15-0206 Contact : olivier.raccurt@cea.fr

Simulation of random nature variability in integrated circuits at architecture level

The current market trend of embedded systems is the development of multiprocessor system on-chip (MPSoC) capable of supporting various applications that are faster (GOps/s), consumes less energy and are less expensive. These applications have a dynamic behaviour since their execution time depends mainly on the input data. Furthermore, these architectures are generally implemented using state of the art technologies in order to benefit from the gain in performance and power offered by the miniaturization of devices. Technology downscaling increases the variability of transistor parameters and temporal variations due to ageing of transistors (e.g. Hot carriers, BTI, etc.) bring up phenomenon that cannot be neglected anymore (e.g. SEB in NMOS). These temporal deviations, which depend on the application can aggravate thermal gradients and be the cause of a system malfunctions. To prevent these effects, CEA LIST has developed software tools, to explore the design space of MPSoC architectures and simulate ageing according to architecture design, applications, technology and temperature. These tools are based on simple models of temporal degradation of the transistors. From the 28nm CMOS node, the transitor parameters temporal deviation becomes random. The physics of failure becomes more complex to understand. These random fluctuations should be taken into account in the simulation to accurately predict system behavior. Based on existing transistor-level ageing models and software tools, the PhD thesis will address the issue related to modeling and simulation at circuit / architecture level of these phenomena with random nature. An expected result will be new prototype ageing simulator. About CEA: The French Alternative Energies and Atomic Energy Commission (CEA) is a major player in the research, development and innovation. This technological research organization active in three main areas: energy, information and communication technologies, health and defense. Acting as high-level expert, CEA is fully inserted into the European Research Area and has a growing international presence. Located at the heart of Saclay area (Paris region), the CEA LIST Institute focuses its research activities on developing innovative technologies for smart and complex systems. Its R&D programs, with potentially major economic and social implications, focus on interactive systems (ambient intelligence), embedded systems (architecture, software and systems engineering), sensors and signal processing (industrial control systems, health, security and metrology).

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire Calcul Embarqué Start Date : 01-09-2015 ECA Code : SL-DRT-15-0274 Contact : olivier.heron@cea.fr

Exploration and optimization of software architecture for real-time embedded applications

In embedded systems, the multitasks conception and execution model is an essential component to correctly design and execute applications. It provides a programming and execution model for the optimal use of the hardware platform. In this context, the fundamental purpose of an execution model based on the Time-Triggered paradigm is to enable the development of temporally deterministic, therefore reproducible, systems. This is enforced by an execution and communication models that ensure end-to-end real-time constraints. Before its execution, a real-time embedded application goes through a step of specification / design using high level abstraction tools and languages such as (SysML, UML / MARTE, MathLab /Similink, Modelica, BIP ...). This produces an application model constructed as a set of functions blocks and, or a pseudo-code, from which a first implementation is generated, and in most cases rewritten manually. During the implementation phase, the developer needs to deal with the complexity of setting up the tasks structure: i.e. how to group the actions/functions blocks in basic thread (task) according to the performance and safety specifications. The implementation strategy is not specified at the specification/design steps, the designer must first deploys the blocks and/or pseudo code into a tasks structure. This deployment is highly dependent on the given communication and synchronization model. Poor control of this step can generate an inefficient tasks model and does not allow to take full benefits of the execution model and hardware platform. The purpose of this PhD thesis is to study "the construction of a real-time applications (multitasking architecture)" starting from a model expressed with a high level specification language. This construction is guided by a multiple-criterion (functional or not) optimization (based on compromise) and taking into account: - Behavioral constraints, structural and real-time constraints as specified in the high level model, - Non-functional constraints, - Specificity of the execution model (RTOS). The obtained multitasks architecture should allow the generation of an executable code with limited effort by using simple language transformations toward the targeted implementation language.

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoires des fondements des systèmes Temps réel Embarqués Start Date : 01-10-2015 ECA Code : SL-DRT-15-0292 Contact : Belgacem.ben-hedia@cea.fr

Radiofrequency receiver based on compress sensing for versatile multi-strandard applications

The aim of the thesis is to develop a radio-frequency receiver based on compressive sensing and evaluate its interest with respect to performance enhancement and/or power consumption reduction in a context of multi-standard applications. Most relevant signals can be compressed: our smartphones are filled with photos taken with cameras of several million pixels, which, after compression occupy only a few thousand bytes. We can wonder what is the interest to get so much large amount of information if only a small part of it is interesting ? The sparse sampling is proposed to answer the question by trying to directly extract the relevant information. The problem is fully transferable to radiofrequency receiver at the core of our mobile radio equipment used dailys. This is called "analog converter to information" rather than "analog to digital converter" to the extent that it seeks to convert the useful rather than the raw signal itself information. From mathematical point of view the principle consists in achieving the correlation of the useful signal with several reference signals and to collect only the result of this correlation. However in the field of radio frequency signals lot's of work remains to be done to determine how to achieve optimal correlation and what are these famous reference signals? The candidate should have a strong background in mathematics and signal processing. On the other hand background in electronics field is mandatory in order to understand the implementation aspect of the proposed solution. To complete the project the candidate will set up a system simulation platform demonstrating the principles and implementation of the proposed solution. A feasibility study will be conducted to evaluate the potential of this new solution.

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire Architectures Intégrées Radiofréquences Start Date : 01-10-2015 ECA Code : SL-DRT-15-0336 Contact : michael.pelissier@cea.fr

CMOS Image sensors embedding in-pixel sensing and energy harvesting capabilities

The aim of this PhD work is to explore new architectures of CMOS Image Sensors dedicated to very low power applications. These sensors will have to be an ultra-low power system with energy harvesting capabilities (photovoltaic mode). Currently, Industrial CMOS Image Sensors propose basically a high resolution (more than Mega pixels) and high level of electro-optical performances. In this context, the power consumption constraint is not a high level of priority. But, currently, new emergent applications such as Wireless Sensor Networks or more general emergent context like IoT (Internet of Things), imply that the sensor is the key element of such event based systems. Moreover, such systems have, by definition, a low level of available energy. This property implies to use Ultra Low Power sensor. In this context, such applications development is highly constrained by the power consumption of industrial image sensors when vision capability is required. The PhD student will study and design an Ultra-Low Power CMOS image Sensor which includes an energy harvesting mode (photovoltaic mode). PhD objectives are to study, design and test a fully functional prototype. This prototype will show scientific and industrial potentialities of such sensor. The PhD candidate will have general skills in microelectronic design, in particular on analog circuit design. Good knowledge in electronic development and semiconductor physics is very important. CAD tools (as Cadence environment) and prototyping environment (FPGA) have to be well known. Knowledge in image processing and associated tool (as Matlab) will be appreciated.

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Département : Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Laboratory : Laboratoire Circuits Intégrés, Intelligents pour l'Image Start Date : 01-09-2015 ECA Code : SL-DRT-15-0384 Contact : gilles.sicard@cea.fr
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