Scientific direction Development of key enabling technologies
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PhD : selection by topics

Engineering science >> Computer science and software
3 proposition(s).

New wake up radio for an energy efficient integration of interacting IoTs in Cyber-Physical Systems

Département Systèmes

Laboratoire Communication des Objets Intelligents

01-09-2018

SL-DRT-18-0693

mickael.maman@cea.fr

With the massive deployment of sensor network applications, long lifetime networks are mandatory and very challenging. To optimize the network lifetime, it is crucial to design ultra-low power communication systems. Several technologies are competing for low power uplink communications (e.g., LoRa, Sigfox, Bluetooth LE, Thread, Zigbee, WiFi). But when interaction with IoT devices is mandatory (e.g., command in Cyber Physical System, interaction with the real environment in Augmented Reality), ultra-low power as well as predictable latency Downlink communications are missing. A lot of efforts were devoted to the design of energy efficient communication protocols, and especially MAC protocols. MACs have a critical role in the energy efficiency of communications as they control the transceiver. The aim of MAC protocols is to allow point-to-point communication between two neighboring nodes. Some technologies (e.g., LoRa, SigFox) proposes to open a window for Downlink communications after each Uplink communication in case of traffic. This approach does not work for latency constraint applications since a Downlink command could be process only after an Uplink communication. Other MAC solutions propose to periodically listen to Another approach is the use of ultra-low power wake-up receivers (WRX) which can significantly reduce the overall power consumption of the system. In this approach, the device can continuously listen to a wake up signal in the channel. The drawbacks of these solutions are their low maturity (proof of concept) and their very low sensitivity. During this PhD, we propose a cross-layer approach (RF/PHY/MAC). Our goal is to make a tradeoff between the energy consumption, the latency and the performance (e.g., range of communication).

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Secure implementation of stream ciphers

Département Systèmes

Laboratoire Sécurité des Objets et des Systèmes Physiques

01-10-2018

SL-DRT-18-0762

mathieu.desnoes@cea.fr

Recent attacks on processors (Meltdown [1] and Spectre [2]) highlight vulnerabilities of hardware circuits for consumer electronics. This applies to PC, laptop and smartphones, but also to small processors integrated in smart devices (Internet of Things). It becomes urgent to secure these processors taking into account theirs specifics contraints (hardware footprint and low power consumption). More specifically, it is required to secure intra-chip communications in order to ensure confidentiality and integrity of data exchanged between a CPU and peripheral (eg. FLASH, DMA, SRAM?.). Stream ciphers [3] are well adapted to meet the above challenge because of their lightweight implementation [4]. The security of the system is however transfered to the implementation of the stream cipher. The goal of this thesis is thus to propose lightweight implementations that are robust to side channel and fault injection attacks. The applicant will propose and implement countermeasures taking into account the constraints imposed by the IoT context: a small amount of hardware ressources, low power consumption and acceptable speed performance. [1] https://meltdownattack.com/meltdown.pdf [2] https://spectreattack.com/spectre.pdf [3] http://www.ecrypt.eu.org/stream/ [4] https://www.cryptolux.org/index.php/Lightweight_Cryptography

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Processors ensuring confidentiality, authenticity and integrity of programs

Département Systèmes

Laboratoire Sécurité des Objets et des Systèmes Physiques

01-12-2018

SL-DRT-18-0965

olivier.savry@cea.fr

Until now, confidentiality, authenticity and integrity have never been shown jointly in modern secure processors, whereas they are essential to guarantee the intellectual property, deployment, safety and reliability of products Industrial objects such as IoT (Internet of Things) or CPS (Cyber Physical Systems). In this thesis, we will seek to ensure the integrity of program execution with authenticated encryption of instructions and lightweight and powerful data from the CAESAR competition. It will be shown that confidentiality can be achieved by these same techniques and that they allow a simple deployment. The correct execution of the flow of instructions will be proved and this until the processing by the ALU using corrector and / or error detection codes. The derived security architecture can then be validated on RISC V on an FPGA target.

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