Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PostDocs : selection by topics

Technological challenges >> New computing paradigms, circuits and technologies, incl. quantum
5 proposition(s).

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Multi-scale modeling of the electromagnetic quantum dot environment

Département Composants Silicium (LETI)

Laboratoire de Simulation et Modélisation

01-03-2021

PsD-DRT-21-0027

helene.jacquinot@cea.fr

In the near future, emerging quantum information technologies are expected to lead to global breakthroughs in high performance computing and secure communication. Among semiconductor approaches, silicon-based spin quantum bits (qubits) are promising thanks to their compactness featuring long coherence time, high fidelity and fast qubit rotation [Maurand2016], [Meunier2019]. A main challenge is now to achieve individual qubit control inside qubit arrays. Qubit array constitutes a compact open system, where each qubit cannot be considered as isolated since it depends on the neighboring qubit placement, their interconnection network and the back-end-line stack. The main goal of this post-doctoral position is to develop various implementation of spin control on 2D qubit array using multi-scale electromagnetic (EM) simulation ranging from nanometric single qubit up to millimetric interconnect network. The candidate will i) characterize radio-frequency (RF) test structures at cryogenic temperature using state-of-the-art equipment and compare results with dedicated EM simulations, ii) evaluate the efficiency of spin control and allow multi-scale optimization from single to qubit arrays [Niquet2020], iii) integrate RF spin microwave control for 2D qubit array using CEA-LETI silicon technologies. The candidate need to have a good RF and microelectronic background and experience in EM simulation, and/or design of RF test structures and RF characterization. This work takes place in a dynamic tripartite collaborative project between CEA-LETI, CEA-IRIG and CNRS-Institut Néel (ERC ?Qucube?).

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Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-01-2020

PsD-DRT-20-0029

francois.andrieu@cea.fr

For integrated circuits to be able to leverage the future ?data deluge? coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this ?memory wall? consists in processing the information in-situ, owing to In-Memory-Computing (IMC). However, today's existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory. The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.

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Digital circuit design for In-Memory Computing in advanced Resistive-RAM NVM technology

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-02-2021

PsD-DRT-21-0049

francois.andrieu@cea.fr

For integrated circuits to be able to leverage the future ?data deluge? coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this ?memory wall? consists in processing the information in-situ, owing to In-Memory-Computing (IMC). CEA-Leti launched a project on this topic, leveraging three key enabling technologies, under development at CEA-Leti: non-volatile resistive memory (RRAM), new energy-efficient nanowire transistors and 3D-monolithic integration [ArXiv 2012.00061]. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems.

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Polar codes for fault tolerant quantum computation

Département Systèmes (LETI)

Laboratoire Sans fils Haut Débit

01-10-2021

PsD-DRT-21-0103

valentin.savin@cea.fr

The last years have seen significant advances in the field of quantum technologies, promising a disruptive impact in information and computing technologies. Nonetheless, for unleashing the full computational power that quantum computers can bring, a critical task is to protect the quantum computation from the inherent quantum noise. This makes quantum error correction (QEC) an essential component of any quantum computer, acting as an interface between physical (noisy) and logical (noiseless) qubits. This project aims at exploring pioneering approaches to fault-tolerant (FT) quantum computation, relying on quantum polar codes. Introduced first in 2009 for classical systems, and then generalized to the quantum case, polar codes arguably represent the most important advance in coding theory of the past decade. They achieve the coherent information (one-shot capacity) of any quantum channel, and come equipped with an efficient decoding algorithm, whose complexity scales log-linearly with the code length. Yet, despite their excellent error correction properties, polar codes have been hardly explored for quantum computing. The main objective of this project is to develop a complete framework of FT quantum computation using quantum polar codes, thus harnessing their unique benefits in terms of error correction capacity, decoding, and structure.

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Scalable digital architecture for Qubits control in Quantum computer

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Silicium des Architectures Numériques

01-01-2021

PsD-DRT-20-0116

eric.guthmuller@cea.fr

Scaling Quantum Processing Units (QPU) to hundreds of Qubits leads to profound changes in the Qubits matrix control: this control will be split between its cryogenic part and its room temperature counterpart outside the cryostat. Multiple constraints coming from the cryostat (thermal or mechanical constraints for example) or coming from Qubits properties (number of Qubits, topology, fidelity, etc?) can affect architectural choices. Examples of these choices include Qubits control (digital/analog), instruction set, measurement storage, operation parallelism or communication between the different accelerator parts for example. This postdoctoral research will focused on defining a mid- (100 to 1,000 Qubits) and long-term (more than 10,000 Qubits) architecture of Qubits control at room temperature by starting from existing QPU middlewares (IBM QISKIT for example) and by taking into account specific constraints of the QPU developed at CEA-Leti using solid-state Qubits.

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