Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PostDocs : selection by topics

Engineering sciences >> Electronics and microelectronics - Optoelectronics
4 proposition(s).

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Ultra Low Power RF Communication Circuit and System Design for Wake-Up Radio

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Architectures Intégrées Radiofréquences

01-01-2019

PsD-DRT-19-0026

dominique.morche@cea.fr

Today, there is a strong demand in developing new autonomous Wake-Up radio systems with tunable performances and independent clocking system. The objectives of the proposed contract it to exploit the capacity of CMOS FD-SOI technologies to develop such devices, improving power consumption and RF performance above the state of the art, thanks to the natural low parasitic and tuning capacity through back biasing of the FD-SOI . A particular attention will be paid to the development of a new power efficient, fast settling, frequency synthesis system. The chosen candidate will be involved both in RF system and circuit design, with the support of the experienced RF System & Design team.

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Innovative modeling for technology-design-system co-optimization

Département Composants Silicium (LETI)

Laboratoire de Simulation et Modélisation

01-01-2019

PsD-DRT-19-0028

luca.lucci@cea.fr

The post-DOC will support the device modeling part of a research project investigating new methodologies for system and circuit optimization with the aim of achieving a better integration between the knowledge of the detailed characteristics of a specific technology, the circuit-design methodology and the system architecture. The practical goal is to leverage the existing multi-disciplinary know-how for benchmarking of system and technologies to advance the analysis past the usual PPA, PPAY and PPAC approaches that are commonly deployed in such cases. In more detail, the post-DOC will develop "pre"-spice models for actives and passives which will constitute the basic bricks for the optimization methodology developed in the overall project. Active device modeling will have a starting point in the works of EPFL based on the analytical expression of invariants such has the inversion coefficient.

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Modeling of trapping and vertical leakage effects in GaN epitaxial substrates on Si

Département Composants Silicium (LETI)

Laboratoire de Simulation et Modélisation

PsD-DRT-20-0043

marie-anne.jaud@cea.fr

State of the art: Understanding and modeling vertical leakage currents and trapping effects in GaN substrates on Si are among the crucial subjects of studies aimed at improving the properties of GaN power components : current collapse and Vth instabilities reductions, reduction of the leakage current in the OFF state. Many universities [Longobardi et al. ISPSD 2017 / Uren et al. IEEE TED 2018 / Lu et al. IEEE TED 2018] and industrials [Moens et al. ISPSD 2017] are trying to model vertical leakages but until now, no clear mechanism has emerged from this work to model them correctly over the entire range of voltage and temperatures targeted. In addition, modeling the effects of traps in the epitaxy is necessary for the establishment of a a robust and predictive TCAD model of device. For LETI, the strategic interest of such a work is twofold: 1) Understanding and reducing the effects of traps in the epitaxy impacting the functioning of GaN devices on Si (current collapse, Vth instabilities?) 2) Reaching the leakage specifications @ 650V necessary for industrial applications. The candidate will have to take charge in parallel of the electrical characterizations and the development of TCAD models: A) Advanced electrical characterizations (I (V), I (t), substrate ramping, C (V)) as a function of temperature and illumination on epitaxial substrates or directly on finite components (HEMT, Diodes, TLM ) B) Establishment of a robust TCAD model integrating the different layers of the epitaxy in order to understand the effects of device instabilities (dynamic Vth, dynamic Ron, BTI) C) Modeling of vertical conduction in epitaxy with the aim of reducing leakage currents at 650V Finally, the candidate must be proactive in improving the different parts of the substrate

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Low temperature process modules for 3d coolcube integration : through the end of roadmap

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-03-2019

PsD-DRT-19-0048

claire.fenouillet-beranger@cea.fr

3D sequential integration is envisaged as a possible solution until the end of CMOS roadmap. Different process modules have been developped @ 500°C for planar FDSOI technology in a gate first process. However, regarding bottom transistor level stability in CoolcubeTM integration, and yield consideration, the need to reduce further the top transistor temperature down to 450°C should be explored. The post-doc will have in charge the development of specific technological modules at low temperature both 500°C and 450°C for FDSOI planar devices to acquire a solid knowledge in low temperature CMOS process integration. The specific low temperature gate module will be addressed on planar devices. The threshold voltage modulation will also be studied. The work will be performed in collaboration with the technological platform process of LETI for the low temperature modules development. The electrical characterization in collaboration with the characterization laboratory and the TCAD simulations team of LETI.

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