Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PostDocs : selection by topics

Engineering science >> Electronics and microelectronics - Optoelectronics
7 proposition(s).

Design for reliability for digital circuits

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Fiabilité et Intégration Capteur

01-03-2018

PsD-DRT-18-0010

valentin.gherman@cea.fr

Flash memories are a key enabler for high-temperature applications such as data acquisition and engine control in aerospace, automotive and drilling industries. Unfortunately, the retention time of flash memories is very sensitive to high temperatures. Even at relatively moderated temperatures, flash memories may be affected by retention-related problems especially if they are set to store more than one bit per cell. This impact can be mitigated by periodically refreshing the stored data. The problem is that, in the presence of a variable operating temperature that could be due to variable environmental and workload conditions, a fixed data-refresh frequency may become disproportionately large with a subsequent impact on response time and cycling endurance. The first objective of this project is to implement a data-refresh method based on a specially designed counter that is able to (a) track the evolution of the temperature and its impact on the data retention time of Flash memory blocks, (b) trigger warnings against potential retention time hazards and (c) provide timestamps. The second objective is to find the distribution law that gives the evolution of the number of data retention errors in time. The goal is to implement a methodology able to infer the remaining retention time of flash memory pages based on their data retention age, i.e., the elapsed time since data was stored, and the number of retention and non-retention errors. The publication of the scientific results in high-ranked conferences and journals is major project objective.

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Ultra Low Power RF Communication Circuit and System Design for Wake-Up Radio

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Architectures Intégrées Radiofréquences

01-01-2019

PsD-DRT-19-0026

dominique.morche@cea.fr

Today, there is a strong demand in developing new autonomous Wake-Up radio systems with tunable performances and independent clocking system. The objectives of the proposed contract it to exploit the capacity of CMOS FD-SOI technologies to develop such devices, improving power consumption and RF performance above the state of the art, thanks to the natural low parasitic and tuning capacity through back biasing of the FD-SOI . A particular attention will be paid to the development of a new power efficient, fast settling, frequency synthesis system. The chosen candidate will be involved both in RF system and circuit design, with the support of the experienced RF System & Design team.

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Nouvelle approche de conception circuits et systèmes en optimisation conjointe avec des technologies en rupture

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Architectures Intégrées Radiofréquences

01-01-2019

PsD-DRT-19-0027

dominique.morche@cea.fr

The objective of this contract is to validate and improve a new system and circuit optimisation approach on different application areas. The candidate will be in charge of creating the architectural model taking into account the different solutions that can be used, starting from the simplest implementation and then adding gradually complexity and precision to the models. The purpose will be to compare the result of the analysis approach to the value obtained on existing systems developped in CEA. For that purpose, the candidate will be jointly working with numerous teams working on technology development, technology modeling and characterization, circuit design and lastly system modeling. To validate the proposed approach, the objective of the candidate will be to test it on three different levels: at basic building block level (lna, ring oscillator) using 22 FDX technology, at function level (front-end module for WiFi) using 130nm PD-SOI and lastly for imagers and mmw radars using 3D technology.

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Innovative modeling for technology-design-system co-optimization

Département Composants Silicium (LETI)

Laboratoire de Simulation et Modélisation

01-01-2019

PsD-DRT-19-0028

luca.lucci@cea.fr

The post-DOC will support the device modeling part of a research project investigating new methodologies for system and circuit optimization with the aim of achieving a better integration between the knowledge of the detailed characteristics of a specific technology, the circuit-design methodology and the system architecture. The practical goal is to leverage the existing multi-disciplinary know-how for benchmarking of system and technologies to advance the analysis past the usual PPA, PPAY and PPAC approaches that are commonly deployed in such cases. In more detail, the post-DOC will develop "pre"-spice models for actives and passives which will constitute the basic bricks for the optimization methodology developed in the overall project. Active device modeling will have a starting point in the works of EPFL based on the analytical expression of invariants such has the inversion coefficient.

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Detection of small particules in the environment with nanomechanical resonators

Département Composants Silicium (LETI)

Laboratoire Composants Micro-Capteurs

01-06-2019

PsD-DRT-19-0033

sebastien.hentz@cea.fr

Today, there are solutions for detecting and quantifying PM10 and PM2.5 type particles (10 and 2.5µm diameter); their reliability depends essentially on their cost. These solutions are essentially optical, and they must be improved for particles down to a micron. For even smaller particles that are even more dangerous to health, there does not seem to be an obvious solution today. Nanomechanical resonators perform very well in these size / mass ranges, as demonstrated by our recent results obtained with our system for biological objects in liquid, recently published by the journal Science (http://science.sciencemag.org/content/ 362/6417/918). These nanoresonators therefore appear as a promising technology for the detection of PM especially for certain applications of air quality control in real time. It will therefore be necessary to study the possibility of detecting particles in the air, in particular those which are hardly detectable today (PM <0.5). We will rely very largely on the systems developed for the detection of biological particles in liquid medium. It will be a question of taking advantage of this know-how and of adapting the system architectures, but also the nanomechanical resonators themselves for the detection of particles in aerosol. We will target representative nanoparticles, organic, pathogenic or non-pathogenic. In terms of resonators, we will also take advantage of current fabrications, with specific designs (electrical or optomechanical) for this application. We will particularly study the possibility of preventing fouling problems. The candidate will be fully integrated into the team around mass detection with nanoresonators.

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Low temperature process modules for 3d coolcube integration : through the end of roadmap

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-03-2019

PsD-DRT-19-0048

claire.fenouillet-beranger@cea.fr

3D sequential integration is envisaged as a possible solution until the end of CMOS roadmap. Different process modules have been developped @ 500°C for planar FDSOI technology in a gate first process. However, regarding bottom transistor level stability in CoolcubeTM integration, and yield consideration, the need to reduce further the top transistor temperature down to 450°C should be explored. The post-doc will have in charge the development of specific technological modules at low temperature both 500°C and 450°C for FDSOI planar devices to acquire a solid knowledge in low temperature CMOS process integration. The specific low temperature gate module will be addressed on planar devices. The threshold voltage modulation will also be studied. The work will be performed in collaboration with the technological platform process of LETI for the low temperature modules development. The electrical characterization in collaboration with the characterization laboratory and the TCAD simulations team of LETI.

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FDSOI technology scaling beyond 10nm node

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-11-2018

PsD-DRT-18-0074

claire.fenouillet-beranger@cea.fr

FDSOI (Fully-Depleted Silicon On Insulator) is acknowledged as a promising technology to meet the requirements of emerging mobile, Internet Of Things (IOT), and RF applications for scaled technological nodes [1]. Leti is a pioneer in FDSOI technology, enabling innovative solutions to support industrial partners. Scaling of FDSOI technology beyond 10nm node offers solid perspectives in terms of SoC and RF technologies improvement. Though from a technological point of view, it becomes challenging because of thin channel thickness scaling limitation around 5nm to maintain both good mobility and variability. Thus, introduction of innovative technological boosters such as strain modules, alternative gate process, parasitics optimization, according to design rules and applications, become mandatory [2]. The viability of these new concepts should be validated first by TCAD simulations and then implemented on our 300mm FDSOI platform. This subject is in line with the recent LETI strategy announcement and investments to develop new technological prototypes for innovative technology beyond 28nm [3]. The candidate will be in charge to perform TCAD simulations, to define experiment and to manage them until the electrical characterization. The TCAD simulations will be performed in close collaboration with the TCAD team. The integration will be done in the LETI clean room in collaboration with the process and integration team. Candidate with out-of-the-BOX thinking, autonomy, and ability to work in team is mandatory. [1] 22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications, R. Carter et al, IEEE IEDM 2016. [2] UTBB FDSOI scaling enablers for the 10nm node, L. Grenouillet et al, IEEE S3S 2013. [3]https://www.usinenouvelle.com/article/le-leti-investit-120-millions-d-euros-dans-sa-salle-blanche-pour-preparer-les-prochaines-innovations-dans-les-puces.

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