Scientific direction Development of key enabling technologies
Transfer of knowledge to industry

PostDocs : selection by topics

Engineering science >> Electronics and microelectronics - Optoelectronics
12 proposition(s).

Design for reliability for digital circuits

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Fiabilité et Intégration Capteur

01-03-2018

PsD-DRT-18-0010

valentin.gherman@cea.fr

Flash memories are a key enabler for high-temperature applications such as data acquisition and engine control in aerospace, automotive and drilling industries. Unfortunately, the retention time of flash memories is very sensitive to high temperatures. Even at relatively moderated temperatures, flash memories may be affected by retention-related problems especially if they are set to store more than one bit per cell. This impact can be mitigated by periodically refreshing the stored data. The problem is that, in the presence of a variable operating temperature that could be due to variable environmental and workload conditions, a fixed data-refresh frequency may become disproportionately large with a subsequent impact on response time and cycling endurance. The first objective of this project is to implement a data-refresh method based on a specially designed counter that is able to (a) track the evolution of the temperature and its impact on the data retention time of Flash memory blocks, (b) trigger warnings against potential retention time hazards and (c) provide timestamps. The second objective is to find the distribution law that gives the evolution of the number of data retention errors in time. The goal is to implement a methodology able to infer the remaining retention time of flash memory pages based on their data retention age, i.e., the elapsed time since data was stored, and the number of retention and non-retention errors. The publication of the scientific results in high-ranked conferences and journals is major project objective.

Frequency tunable elastic plate wave resonators and filters

Département Composants Silicium (LETI)

Laboratoire Composants Radiofréquences

01-03-2017

PsD-DRT-17-0011

alexandre.reinhardt@cea.fr

The increasing number of frequency bands having to be dealt with in mobile phone systems require a huge number of band pass filters in such systems. In this context, the capability to provide frequency tunable resonators and filters is seen as a key enabling element in future wireless transmission systems. CEA-LETI has been working for more than 10 years on the development of resonators and filters exploiting the propagation of guided elastic waves in piezoelectric thin films. It has also proposed several concepts for frequency agile resonators and filters. The purpose of this post-doc will be to further develop these ideas and to apply them to the design of demonstrators matching realistic specifications. In collaboration with the other member of the project team, more focused on fabrication in clean rooms, the candidate will propose innovative structures demonstrating frequency tuning of reconfigurability, and will take in charge their electrical characterization.

Design / Technology Co-Optimization of SRAM and standard cells on stacked nanowires at the 5nm technology node

Archive des laboratoires DRT (ne pas utiliser)

Laboratoire Dispositifs Innovants

01-02-2017

PsD-DRT-17-0013

francois.andrieu@cea.fr

The post-doctoral position will focus on the layout of SRAM and standard cells dedicated to the 5nm node on stacked nanowires integrating a Direct Self-Assembly solution (DSA). He/she will use the SPICE model developed at LETI and interact with both model and process/integration teams to find the best layout for a set of cells.

Optimisation of the monolithic cascode device based on GaN/Si MOS-Channel HEMT technology

Département Composants Silicium (LETI)

Laboratoire Composants Electroniques pour l'Energie

01-02-2017

PsD-DRT-17-0017

erwan.morvan@cea.fr

In order to adress the requirements of power conversion in the field of electrical vehicule or photovoltaics, high performance GaN on Silicon power devices need to be developped. Such power devices must fulfill agressive specifications in terms of threshold voltage (> 2V), nominal current (100-200A), breakdown voltage (650 and 1200V) and stability (low "current collapse", low hysteresis). Discrete cascode configuration, consisting in a combination of a low voltage E-mode Silicon die and a hihg voltage D-mode GaN/Si die in a single package, has been developped by different laboratories and companies to adress this need (Transphorm, On-Semi, NXP, IR?). However, this approach has some drawbacks like parasitic inductances, device pairing, need of additionnal protection devices, cost, temperature limitation due to the Si die... The monolithic cascode is a very compact version of the cascode configuration that will allow to avoid those problems but also to improve the performance of E-mode devices developped at Leti (MOS-channel HEMT). Indeed, some actors in the field of GaN power devices already use this configuration with another E-mode technology (p-GaN gate). Monolithic cascode device has been demonstrated recently by CEA-Leti in the frame of a PhD thesis (2014-2016) on the basis of the 200mm GaN/Si, CMOS compatible, MOS-channel HEMT technology. The aim of this post-doc is to optimize the monolithic cascode structure in terms of On-state resistance, Figure Of Merit, switching losses and high switching frequency capability in order to meet the specifications of our industrial partners.

Minimizing modifications at III-V pattern sidewalls after plasma etching for heterointegrated optoelectronics and nonlinear photonics

Département Technologies Silicium (LETI)

Autre laboratoire

01-03-2017

PsD-DRT-17-0032

eugenie.martinez@cea.fr

This project will focus on understanding plasma-induced damage at the sidewalls of micro-nano-patterned III-V semiconductors to find relevant technological solutions capable to minimize this damage. There is a clear need of knowledge on by which mechanisms and to what extent the plasma etching process modifies the III-V pattern sidewalls and the consequences it has on the device optical performances. The selected III-V semiconductor will be aluminium gallium arsenide which exhibits excellent optoelectronic properties and strong nonlinear parametric gain. The student will be mainly focused on understanding how the key plasma process parameters influence the structural and chemical changes at the III-V sidewalls, as well as changes of optical properties. This will require the development of a methodology for a 3D quantitative characterization of the sidewalls at the nanoscale, based on Auger microscopy and cathololuminescence. The main objective will be to correlate plasma-induced structural defects and modifications of the optoelectronics properties. The second step will consist in developing optimized plasma etching processes for III-V semiconductors, exploring alternative plasma technologies. You will also be involved in the development of processes for restoring and passivating the AlGaAs sidewalls.

Design of a power integrated circuit using GaN on Si, characterization, implementation.

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

01-03-2017

PsD-DRT-17-0038

dominique.bergogne@cea.fr

The objective is to propose an innovative solution to supply low voltage electronics (3 to 12VDC) or to charge accumulators, using industrial alternating voltages (230VAC / 400VAC). This type of device should benefit greatly from the contribution of integrated passive technologies and the possibilities offered by the ASICs developed at Leti, in particular GaN ASICs. This research program is part of the Leti's 'power roadmap'. From the state of the art and concepts envisaged by CEA researchers, the post-doctoral student will have to imagine an original solution, to design it and then to characterize the prototype. The research program involves other academic partners, which allows the post-doctoral student to immerse himself in an upstream research context. An industrial application has been identified. The post-doctoral student will be encouraged to enrich the subject with additional functions in the control (regulation) at very high frequency, the transmission of isolated signals via the converter or any other proposals.

2D materials for Contacts and Gate stacks for advanced CMOS applications

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-06-2017

PsD-DRT-17-0039

louis.hutin@cea.fr

Transition Metal Dicalchogenides (TMDs) have displayed interesting properties in numerous fields of nanotechnoogy (CMOS, memory, sensors, photonics etc.), and emerge as promising materials thanks to their functional properties and potential for co-integration, facilitated by their intrinsic features (van der Waals materials). However, their applicative impact remains uncertain due to the challenge of developing their processing in a standard nanoelectronics environment while maintaining a good control of their fundamental properties. The candidate will quantify the electrical properties of various 2D materials in test structures derived from a silicon technology baseline (TLM, Cross-Bridge Kelvin Résistors, MOS capacitors), in order to provide guidelines for device prototyping. Specifically, the primary aim is to assess the interest of these materials as interface layers rather than for transport, for improving: - The contact resistivity via Fermi-level depinning. - Control by the Gate over the inversion charge in the channel via a negative differential capacitance effect.

Cryogenic Analog Front-End for Quantum Computing

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

01-02-2018

PsD-DRT-18-0041

gael.pillonnet@cea.fr

Quantum engineering is a rapidly evolving novel domain in device technology, boosted by the recent progress in semiconductor quantum bits (QuBits) and by the major opportunity to combine the quantum device with dedicated electronics of conventional CMOS technology working at low temperatures (= 4 K). The ultimate goal of the research related to the proposed post-doc will be the development of silicon-based systems containing many QuBits and versatile electronics based on mature industrial technology, in order to facilitate the massive introduction of quantum processors. Nowadays state-of-the-art experiments on low-temperature quantum devices use electronic components at room temperature, but the future development of integrating many QuBits together complicates the device control with the multiplication of data lines. Minimal power dissipation and noise characteristics will be the challenging key elements to control a large number of QuBits. At CEA Grenoble, we have developed the first semiconductor QuBit fully realized on a CMOS 300-mm foundry that uses the spins of holes in Si as quantum state. The subject of the post PhD is aimed to build the electronics needed nearby the QuBit at low temperatures, using industrial CMOS technology (FDSOI 28nm) compatible with Silicon Qubits. The post PhD will be asked to develop his competence in the quantum physics of QuBits, the modelling of transistor parameters at low temperatures, and the design and measurement of analogue electronics, with the main task in developing and testing CMOS circuitry at low temperatures.

Feasability study and development of models towards SPICE-simulation of silicon Qubit quantum circuits

Département Composants Silicium (LETI)

Laboratoire de Simulation et Modélisation

01-08-2019

PsD-DRT-18-0056

sebastien.martinie@cea.fr

The Compact / SPICE model is the link between the development of technological bricks and circuit design. The model purpose is to accurately reproduce the experimental characteristics essential to digital, analog and mixed circuit design. But today we need deeper investigation to set up the specifications of models for such device, in order to provide adequate tools to help circuit designers building up quantum circuits. The main challenge is to be able to describe the quantum behavior of this architecture. It will also be necessary to study if this behavior must be described via the physical quantities (eg electronic spin, energy level ...) or by logical quantities (quantum state, matrix of transformation, ...). It will also be necessary to take into account the compatibility between the mathematical formalism and the standard tools of compact modeling (through Verilog-A description). Following recent experimental research activities (between CEA and CNRS) concerning the first demonstration of hole spin qubit on SOI, we propose first to investigate how to model such device through macro modeling approach where SET compact model, inclusion of magnetic spin degeneracy and management of RF excitation are main steps. The challenges in regards to literature are inclusion of magnetic field in SET model, description of resonant tunneling, RF excitation of SET and reproduction of Rabi oscillations.

FDSOI technology scaling beyond 10nm node

Département Composants Silicium (LETI)

Laboratoire d'Intégration des Composants pour la Logique

01-11-2018

PsD-DRT-18-0074

claire.fenouillet-beranger@cea.fr

FDSOI (Fully-Depleted Silicon On Insulator) is acknowledged as a promising technology to meet the requirements of emerging mobile, Internet Of Things (IOT), and RF applications for scaled technological nodes [1]. Leti is a pioneer in FDSOI technology, enabling innovative solutions to support industrial partners. Scaling of FDSOI technology beyond 10nm node offers solid perspectives in terms of SoC and RF technologies improvement. Though from a technological point of view, it becomes challenging because of thin channel thickness scaling limitation around 5nm to maintain both good mobility and variability. Thus, introduction of innovative technological boosters such as strain modules, alternative gate process, parasitics optimization, according to design rules and applications, become mandatory [2]. The viability of these new concepts should be validated first by TCAD simulations and then implemented on our 300mm FDSOI platform. This subject is in line with the recent LETI strategy announcement and investments to develop new technological prototypes for innovative technology beyond 28nm [3]. The candidate will be in charge to perform TCAD simulations, to define experiment and to manage them until the electrical characterization. The TCAD simulations will be performed in close collaboration with the TCAD team. The integration will be done in the LETI clean room in collaboration with the process and integration team. Candidate with out-of-the-BOX thinking, autonomy, and ability to work in team is mandatory. [1] 22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications, R. Carter et al, IEEE IEDM 2016. [2] UTBB FDSOI scaling enablers for the 10nm node, L. Grenouillet et al, IEEE S3S 2013. [3]https://www.usinenouvelle.com/article/le-leti-investit-120-millions-d-euros-dans-sa-salle-blanche-pour-preparer-les-prochaines-innovations-dans-les-puces.

Hardening energy efficient security features for the IoT in FDSOI 28nm technology

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Intégration Silicium des Architectures Numériques

01-10-2017

PsD-DRT-17-0098

simone.bacles-min@cea.fr

The security of the IoT connected objects must be energy efficient. But most of the work around hardening by design show an additional cost, a multiplying factor of 2 to 5, on the surface, performance, power and energy, which does not meet the constraints of the IoT. Last 5 years research efforts on hardening have been guided by reducing silicon area or power, which do not always imply a decrease in energy, predominant criterion in autonomous connected objects. The postdoc topic addresses the hardening and energy consumption optimization of the implementation of security functions (attack detection sensors, cryptographic accelerator, random number generator, etc.) in 28nm FDSOI technology. From the selection of existing security bricks, unhardened in FPGA technology, the postdoc will explore hardening solutions at each step of the design flow in order to propose and to validate, into a silicon demonstrator, the most energy efficient countermeasures that guarantee a targeted security level. To achieve those goals, the postdoc can rely on existing methodologies of design and of security evaluation thanks to test benches and attack tools.

Study of substrate coupling in millimeter wireless circuits

Département Architectures Conception et Logiciels Embarqués (LIST-LETI)

Laboratoire Architectures Intégrées Radiofréquences

01-01-2018

PsD-DRT-17-0125

emeric.defoucauld@cea.fr

The candidate will study substrate coupling in millimeter wireless circuit. He will demonstrate the influence of silicon substrate on millimeter circuit design The first task will consist in establishing the state of the art of substrate reduction technics on millimeter chip. The influence between building blocks at layout level will be analyzed. Parasitic noise effects, frequency and power spurious will be studied with coupling substrate tool. Specifications for layout design in order to reduce spurious will be done, especially for power, analog and digital applications. A design methodology will be proposed with this results.

Voir toutes nos offres